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PDF TMPE633 Data sheet ( Hoja de datos )
| Número de pieza | TMPE633 | |
| Descripción | Reconfigurable FPGA | |
| Fabricantes | TEWS | |
| Logotipo |  |
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The Embedded I/O Company
TMPE633
Reconfigurable FPGA with Digital I/O PCIe Mini Card
Version 1.0
User Manual
Issue 1.0.0
December 2015
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7 25469 Halstenbek, Germany
Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19
1 page  
List of Figures
FIGURE 1-1 : BLOCK DIAGRAM......................................................................................................................6
FIGURE 4-1 : TTL I/O INTERFACE ................................................................................................................13
FIGURE 4-2 : DIFFERENTIAL I/O INTERFACE.............................................................................................15
FIGURE 7-1 : I/O CONNECTOR OVERVIEW ................................................................................................18
FIGURE 7-2 : PRELIMINARY SYSTEM CONNECTOR PIN ASSIGNMENT .................................................19
FIGURE 7-3 : I/O CONNECTOR PIN ASSIGNMENT.....................................................................................20
FIGURE 7-4 : XRS CONNECTOR PIN ASSIGNMENT ..................................................................................21
List of Tables
TABLE 2-1 : TECHNICAL SPECIFICATION.....................................................................................................7
TABLE 4-1 : TMPE633 FPGA FEATURE OVERVIEW....................................................................................9
TABLE 4-2 : FPGA BANK USAGE...................................................................................................................9
TABLE 4-3 : MGT CONNECTIONS ...............................................................................................................10
TABLE 4-4 : MULTI GIGABIT TRANSCEIVER REFERENCE CLOCKS ......................................................10
TABLE 4-5 : FPGA SPI-FLASH CONNECTIONS..........................................................................................10
TABLE 4-6 : AVAILABLE FPGA CLOCKS.....................................................................................................11
TABLE 4-7 : DIGITAL I/O INTERFACE..........................................................................................................13
TABLE 4-8 : I/O PULL OPTIONS...................................................................................................................14
TABLE 4-9 : I/O PULL CONFIGURATION.....................................................................................................14
TABLE 4-10: FPGA GENERAL PURPOSE I/O .............................................................................................15
TMPE633 User Manual Issue 1.0.0
Page 5 of 25
5 Page 
4.3.2 Configuration via JTAG
For direct FPGA configuration, FPGA read back or in-system diagnostics with ChipScope, the JTAG
connector can be used to access the FPGA JTAG port. Also an indirect SPI-Flash programming is possible
via the JTAG Chain.
4.3.3 Generate Spartan-6 Configuration Data
To use the maximum configuration speed, the TMPE633 must be configured to use the 40 MHz external
master clock as CCLK.
To use this configuration feature, the following configuration option must be set:
‘Enable External Master Clock’ (-g ExtMasterCclk_en)
= enable
‘Setup External Master Clock Devision’ (-g ExtMasterCclk_divide)
=1
To use the maximum data transfer speed of the User FPGA SPI Configuration Flash the SPI Configuration
Bus Width must be set to the x4.
‘Set SPI Configuration Bus Width’ (-g SPI_buswidth)
=4
Without this option, the configuration time for the Spartan-6 FPGA exceed the maximum PCIe bus setup
time.
4.4 Clocking
4.4.1 FPGA Clock Sources
The following table lists the available clock sources on the TMPE633:
FPGA Clock-Pin Name
MGTREFCLK0_101
IO_L30N_GCLK0_USERCCLK_2
FPGA Pin
Number
B8 / A8
V10
Source
PCI Express Mini Card
Slot
External oscillator
Table 4-6 : Available FPGA clocks
Description
100 MHz
PCIe Reference clock
40 MHz
Used for external configuration
clock (CCLK)
TMPE633 User Manual Issue 1.0.0
Page 11 of 25
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet TMPE633.PDF ] | |
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