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PE43601 の電気的特性と機能

PE43601のメーカーはPeregrine Semiconductorです、この部品の機能は「RF Digital Attenuator」です。


製品の詳細 ( Datasheet PDF )

部品番号 PE43601
部品説明 RF Digital Attenuator
メーカ Peregrine Semiconductor
ロゴ Peregrine Semiconductor ロゴ 




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PE43601 Datasheet, PE43601 PDF,ピン配置, 機能
Product Description
The PE43601 is a HaRP-enhanced, high linearity, 6-bit RF
Digital Step Attenuator (DSA). This highly versatile DSA
covers a 15.75 dB attenuation range in 0.25 dB steps. The
Peregrine 50RF DSA provides a serial-addressable CMOS
control interface. It maintains high attenuation accuracy over
frequency and temperature and exhibits very low insertion loss
and low power consumption. Performance does not change
with VDD due to on-board regulator. This next generation
Peregrine DSA is available in a 5x5 mm 32-lead QFN footprint.
The PE43601 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Figure 1. Package Type
32-lead 5x5x0.85 mm QFN Package
Product Specification
PE43601
50 RF Digital Attenuator
6-bit, 15.75 dB, 9 kHz - 6.0 GHz
Features
HaRP™-enhanced UltraCMOS™ device
Attenuation: 0.25 dB steps to 15.75 dB
High Linearity: Typical +58 dBm IIP3
Excellent low-frequency performance
3.3 V or 5.0 V Power Supply Voltage
Fast switch settling time
Programming Modes:
Direct Parallel
Latched Parallel
Serial-Addressable: Program up to
eight addresses 000 - 111
Serial Two-Byte Protocol: Address and
Data Word
High-attenuation state @ power-up (PUP)
CMOS Compatible
No DC blocking capacitors required
Packaged in a 32-lead 5x5x0.85 mm QFN
Figure 2. Functional Schematic Diagram
RF Input
Switched Attenuator Array
RF Output
Parallel Control 6
Serial In
CLK
LE
Control Logic Interface
A0 A1
Document No. 70-0253-05 www.psemi.com
A2
P/S
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 13

1 Page





PE43601 pdf, ピン配列
PE43601
Product Specification
Figure 7. Insertion Loss vs. Temperature
-40C
+25C
+85C
0
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
-4
-4.5
-5
01234 5678
Frequency (GHz)
9
Figure 8. Input Return Loss vs. Attenuation:
T = +25C
0dB 0.25dB
0.5dB
2dB 4dB 8dB
0
1dB
15.75dB
-10
-20
-30
-40
-50
-60
-70
012345678
Frequency (GHz)
9
Figure 9. Output Return Loss vs. Attenuation:
T = +25C
0dB
0.25dB
0.5dB
1dB
0 2dB 4dB 8dB 15.75dB
-10
-20
-30
-40
-50
-60
01 23 45 67 89
Frequency (GHz)
Figure 11. Output Return Loss vs. Temperature:
15.75 dB State
-40C 25C 85C
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
0 1234 5 67 89
Frequency (GHz)
Document No. 70-0253-05 www.psemi.com
Figure 10. Input Return Loss vs. Temperature:
15.75 dB State
-40C 25C 85C
0
-10
-20
-30
-40
-50
-60
-70
012 3456789
Frequency (GHz)
Figure 12. Relative Phase vs. Frequency
40
35
30
25
20
15
10
5
0
0
0dB
2dB
12
0.25dB
4dB
0.5dB
8dB
1dB
15.75dB
3 45 67
Frequency (GHz)
8
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 13


3Pages


PE43601 電子部品, 半導体
PE43601
Product Specification
Table 3. Operating Ranges
Parameter
Min Typ
Max Units
VDD Power Supply Voltage 3.0 3.3
V
VDD Power Supply Voltage
IDD Power Supply Current
5.0 5.5
70 350
V
µA
Digital Input High
2.6
PIN Input power (50):
9 kHz 20 MHz
20 MHz 6 GHz
TOP Operating temperature
range
-40
Digital Input Low
0
5.5 V
See fig. 19 dBm
+23 dBm
25 85 °C
1V
Digital Input Leakage1
15 µA
Note 1. Input leakage current per Control pin
Table 4. Absolute Maximum Ratings
Symbol Parameter/Conditions
Min
Max Units
VDD Power supply voltage
-0.3 6.0
V
VI Voltage on any Digital input -0.3
5.8
V
Input power (50)
PIN 9 kHz 20 MHz
20 MHz 6 GHz
See fig. 19 dBm
+23 dBm
TST Storage temperature range
-65
150
°C
VESD
ESD voltage (HBM)1
ESD voltage (Machine Model)
500 V
100 V
Note: 1. Human Body Model (HBM, MIL_STD 883 Method 3015.7)
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted to
the limits in the Operating Ranges table. Operation
between operating range maximum and absolute
maximum for extended periods may reduce reliability.
Figure 19. Maximum Power Handling Capability: Z0 = 50
30.0
25.0
20.0
15.0
10.0
5.0
0.0
1.0E+03
1.0E+04
1.0E+05
1.0E+06
Hz
1.0E+07
1.0E+08
1.0E+09
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 6 of 13
Document No. 70-0253-05 UltraCMOS™ RFIC Solutions

6 Page



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