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PDF LTC1407 Data sheet ( Hoja de datos )
| Número de pieza | LTC1407 | |
| Descripción | Simultaneous Sampling ADCs | |
| Fabricantes | Linear | |
| Logotipo |  |
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FEATURES
n 3Msps Sampling ADC with Two Simultaneous
Differential Inputs
n 1.5Msps Throughput per Channel
n Low Power Dissipation: 14mW (Typ)
n 3V Single Supply Operation
n 2.5V Internal Bandgap Reference with External
Overdrive
n 3-Wire Serial Interface
n Sleep (10μW) Shutdown Mode
n Nap (3mW) Shutdown Mode
n 80dB Common Mode Rejection at 100kHz
n 0V to 2.5V Unipolar Input Range
n Tiny 10-Lead MS Package
APPLICATIONS
n Telecommunications
n Data Acquisition Systems
n Uninterrupted Power Supplies
n Multiphase Motor Control
n I and Q Demodulation
n Industrial Control
LTC1407/LTC1407A
Serial 12-Bit/14-Bit, 3Msps
Simultaneous Sampling
ADCs with Shutdown
DESCRIPTION
The LTC®1407/LTC1407A are 12-bit/14-bit, 3Msps ADCs
with two 1.5Msps simultaneously sampled differential
inputs. The devices draw only 4.7mA from a single 3V
supply and come in a tiny 10-lead MS package. A Sleep
shutdown feature lowers power consumption to 10μW.
The combination of speed, low power and tiny package
makes the LTC1407/LTC1407A suitable for high speed,
portable applications.
The LTC1407/LTC1407A contain two separate differential
inputs that are sampled simultaneously on the rising edge
of the CONV signal. These two sampled inputs are then
converted at a rate of 1.5Msps per channel.
The 80dB common mode rejection allows users to eliminate
ground loops and common mode noise by measuring
signals differentially from the source.
The devices convert 0V to 2.5V unipolar inputs differentially.
The absolute voltage swing for CH0+, CH0–, CH1+ and
CH1– extends from ground to the supply voltage.
The serial interface sends out the two conversion results in 32
clocks for compatibility with standard serial interfaces.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 6084440, 6522187.
BLOCK DIAGRAM
10μF 3V
CH0+
CH0–
CH1+
CH1–
10μF
1+
S AND H
2–
4+
S AND H
5–
3 VREF
GND
6
11 EXPOSED PAD
7
VDD
MUX
3Msps
14-BIT ADC
2.5V
REFERENCE
LTC1407A
THREE-
STATE
SERIAL
OUTPUT
PORT
8 SDO
TIMING
LOGIC
10 CONV
9 SCK
1407A BD
–44
–50
–56
–62
–68
–74
–80
–86
–92
–98
–104
0.1
THD, 2nd and 3rd
vs Input Frequency
THD
2nd
3rd
1 10
FREQUENCY (MHz)
100
1407 G02
1407fb
1
1 page  
LTC1407/LTC1407A
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VDD = 3V.
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX
UNITS
t7 32nd SCK↑ to CONV↑ Interval (Affects Acquisition Period) (Notes 6, 7, 13)
45
ns
t8
Minimum Delay from SCK to Valid Bits 0 Through 11
(Notes 6, 12)
t9 SCK to Hi-Z at SDO
(Notes 6, 12)
t10 Previous SDO Bit Remains Valid After SCK
(Notes 6, 12)
t12 VREF Settling Time After Sleep-to-Wake Transition
(Notes 6, 14)
8
6
2
2
ns
ns
ns
ms
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground GND.
Note 3: When these pins are taken below GND or above VDD, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than VDD without latchup.
Note 4: Offset and range specifications apply for a single-ended CH0+ or CH1+
input with CH0– or CH1– grounded and using the internal 2.5V reference.
Note 5: Integral linearity is tested with an external 2.55V reference and is
defined as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band.
Note 6: Guaranteed by design, not subject to test.
Note 7: Recommended operating conditions.
Note 8: The analog input range is defined for the voltage difference
between CH0+ and CH0– or CH1+ and CH1–.
Note 9: The absolute voltage at CH0+, CH0–, CH1+ and CH1– must be
within this range.
Note 10: If less than 3ns is allowed, the output data will appear one
clock cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11: Not the same as aperture delay. Aperture delay (1ns) is the
difference between the 2.2ns delay through the sample-and-hold and the
1.2ns CONV to Hold mode delay.
Note 12: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13: The time period for acquiring the input signal is started by the
32nd rising clock and it is ended by the rising edge of CONV.
Note 14: The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10μF capacitive load.
Note 15: The full power bandwidth is the frequency where the output code
swing drops by 3dB with a 2.5VP-P input sine wave.
Note 16: Maximum clock period guarantees analog performance during
conversion. Output data can be read with an arbitrarily long clock period.
Note 17: The LTC1407A is measured and specified with 14-bit resolution
(1LSB = 152μV) and the LTC1407 is measured and specified with 12-bit
resolution (1LSB = 610μV).
TYPICAL PERFORMANCE CHARACTERISTICS VDD = 3V, TA = 25°C (LTC1407A)
ENOBs and SINAD
vs Input Sinewave Frequency
12.0
74
11.5 71
11.0 68
10.5 65
10.0 62
9.5 59
9.0 56
8.5 53
8.0
0.1
1 10
FREQUENCY (MHz)
50
100
1407 G01
THD, 2nd and 3rd
vs Input Frequency
–44
–50
–56 THD
2nd
–62
–68
3rd
–74
–80
–86
–92
–98
–104
0.1
1 10
FREQUENCY (MHz)
100
1407 G02
SFDR vs Input Frequency
104
98
92
86
80
74
68
62
56
50
44
0.1
1 10
FREQUENCY (MHz)
100
1407 G19
1407fb
5
5 Page 
LTC1407/LTC1407A
APPLICATIONS INFORMATION
DRIVING THE ANALOG INPUT
The differential analog inputs of the LTC1407/LTC1407A are
easy to drive. The inputs may be driven differentially or as
a single-ended input (i.e., the CH0– input is grounded). All
four analog inputs of both differential analog input pairs,
CH0+ with CH0– and CH1+ with CH1–, are sampled at the
same instant. Any unwanted signal that is common to
both inputs of each input pair will be reduced by the com-
mon mode rejection of the sample-and-hold circuit. The
inputs draw only one small current spike while charging
the sample-and-hold capacitors at the end of conversion.
During conversion, the analog inputs draw only a small
leakage current. If the source impedance of the driving
circuit is low, then the LTC1407/LTC1407A inputs can be
driven directly. As source impedance increases, so will
acquisition time. For minimum acquisition time with high
source impedance, a buffer amplifier must be used. The
main requirement is that the amplifier driving the analog
input(s) must settle after the small current spike before
the next conversion starts (settling time must be 39ns for
full throughput rate). Also keep in mind, while choosing
an input amplifier, the amount of noise and harmonic
distortion added by the amplifier.
CHOOSING AN INPUT AMPLIFIER
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a low
output impedance (< 100Ω) at the closed-loop bandwidth
frequency. For example, if an amplifier is used in a gain
of 1 and has a unity-gain bandwidth of 50MHz, then the
output impedance at 50MHz must be less than 100Ω.
The second requirement is that the closed-loop band-
width must be greater than 40MHz to ensure adequate
small-signal settling for full throughput rate. If slower op
amps are used, more time for settling can be provided by
increasing the time between conversions. The best choice
for an op amp to drive the LTC1407/LTC1407A depends
on the application. Generally, applications fall into two
categories: AC applications where dynamic specifications
are most critical and time domain applications where DC
accuracy and settling time are most critical. The following
list is a summary of the op amps that are suitable for driv-
ing the LTC1407/LTC1407A. (More detailed information
is available in the Linear Technology Databooks and on
the LinearView™ CD-ROM.)
LTC1566-1: Low Noise 2.3MHz Continuous Time Low-
pass Filter.
LT®1630: Dual 30MHz Rail-to-Rail Voltage FB Amplifier.
2.7V to ±15V supplies. Very high AVOL, 500μV offset and
520ns settling to 0.5LSB for a 4V swing. THD and noise
are – 93dB to 40kHz and below 1LSB to 320kHz (AV = 1,
2VP-P into 1kΩ, VS = 5V), making the part excellent for
AC applications (to 1/3 Nyquist) where rail-to-rail perfor-
mance is desired. Quad version is available as LT1631.
LT1632: Dual 45MHz Rail-to-Rail Voltage FB Amplifier.
2.7V to ±15V supplies. Very high AVOL, 1.5mV offset and
400ns settling to 0.5LSB for a 4V swing. It is suitable for
applications with a single 5V supply. THD and noise are
– 93dB to 40kHz and below 1LSB to 800kHz (AV = 1,
2VP-P into 1kΩ, VS = 5V), making the part excellent for
AC applications where rail-to-rail performance is desired.
Quad version is available as LT1633.
LT1801: 80MHz GBWP, –75dBc at 500kHz, 2mA/ampli-
fier, 8.5nV/√Hz.
LT1806/LT1807: 325MHz GBWP, –80dBc distortion at
5MHz, unity-gain stable, rail-to-rail in and out, 10mA/am-
plifier, 3.5nV/√Hz.
LT1810: 180MHz GBWP, –90dBc distortion at 5MHz,
unity-gain stable, rail-to-rail in and out, 15mA/amplifier,
16nV/√Hz.
LinearView is a trademark of Linear Technology Corporation.
1407fb
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LTC1407.PDF ] | |
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