ST92F150JDV1 Datasheet PDF - STMicroelectronics
| Part Number | ST92F150JDV1 | |
| Description | 8/16-bit single voltage Flash MCU | |
| Manufacturers | STMicroelectronics | |
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ST92F124xx/ST92F150Cxx/
ST92F150JDV1/ST92F250CV2
8/16-bit single voltage Flash MCU family with RAM,
E³ TM (emulated EEPROM), CAN 2.0B and J1850 BLPD
Datasheet − production data
Features
■ Memories
– Internal memory: Single Voltage Flash up to 256
Kbytes, RAM up to 8 Kbytes, 1 Kbyte E3 TM
(Emulated EEPROM)
– In-Application Programming (IAP)
– 224 general purpose registers (register file)
available as RAM, accumulators or index
pointers
■ Clock, reset and supply management
– Register-oriented 8/16 bit CORE with RUN,
WFI, SLOW, HALT and STOP modes
– 0-24 MHz Operation (Int. Clock), 4.5-5.5 V
range
– PLL Clock Generator (3-5 MHz crystal)
– Minimum instruction time: 83 ns (24 MHz int.
clock)
■ Up to 80 I/O pins
■ Interrupt management
– 4 external fast interrupts + 1 NMI
– Up to 16 pins programmable as wake-up or
additional external interrupt with multi-level
interrupt handler
■ DMA controller for reduced processor overhead
■ Timers
– 16-bit Timer with 8-bit Prescaler, and Watchdog
Timer (activated by software or by hardware)
– 16-bit Standard Timer that can be used to
generate a time base independent of PLL Clock
Generator
– Two 16-bit independent Extended Function
Timers (EFTs) with Prescaler, up to two Input
Captures and up to two Output Compares
– Two 16-bit Multifunction Timers, with Prescaler,
up to two Input Captures and up to two Output
Compares
■ Communication interfaces
– Serial Peripheral Interface (SPI) with selectable
Master/Slave mode
LQFP64
14x14
PQFP100
14x20
LQFP100
14x14
– One Multiprotocol Serial Communications
Interface with asynchronous and synchronous
capabilities
– One asynchronous Serial Communications
Interface with 13-bit LIN Synch Break
generation capability
– J1850 Byte Level Protocol Decoder (JBLPD)
– Up to two full I²C multiple Master/Slave
Interfaces supporting Access Bus
– Up to two CAN 2.0B Active interfaces
■ Analog peripheral (low current coupling)
– 10-bit A/D Converter with up to 16 robust input
channels
■ Development tools
– Free High performance development
environment (IDE) based on Visual Debugger,
Assembler, Linker, and C-Compiler; Real Time
Operating System (OSEK OS, CMX) and CAN
drivers
– Hardware emulator and Flash programming
board for development and ISP Flasher for
production
Table 1. Device summary
Reference
Part number
ST92F124xx
ST92F150Cxx
ST92F150JDxx
ST92F250Cxx
ST92F124R1, ST92F124R9,
ST92F124V1
ST92F150CR1, ST92F150CR9,
ST92F150CV1, ST92F150CV9
ST92F150JDV1
ST92F250CV2
July 2012
This is information on a product in full production.
Doc ID 8848 Rev 7
1/523
www.st.com
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ST92F124xx/ST92F150Cxx/ST92F150JDV1/ST92F250CV2
Contents
11.1
11.2
11.3
11.4
11.5
11.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Clock control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
11.2.1 Clock control unit overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
11.3.1 PLL clock multiplier programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
11.3.2 PLL free running mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
11.3.3 CPU clock prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
11.3.4 Peripheral clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
11.3.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
11.3.6 Interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Clock control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Reset/stop manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
11.6.1 Reset pin timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
12 External memory interface (EXTMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
12.2 External memory signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
12.2.1
12.2.2
12.2.3
12.2.4
12.2.5
12.2.6
AS: Address strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
DS: Data strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
RW: Read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
DS2: Data strobe 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
PORT 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
PORT 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
12.2.7 PORT 9 [7:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
12.2.8 WAIT: External memory wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
12.3 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
13 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
13.2 Specific port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
13.3 Port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
13.4 Input/output bit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
13.5 Alternate function architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
13.5.1 Pin declared as I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
13.5.2 Pin declared as an alternate function input . . . . . . . . . . . . . . . . . . . . . 200
Doc ID 8848 Rev 7
5/523
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