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PDF COP8SA Data sheet ( Hoja de datos )
| Número de pieza | COP8SA | |
| Descripción | 8-Bit CMOS ROM Based and One-Time Programmable OTP Microcontroller with 1k to 4k Memory/ Power On Reset/ and Very Small Packaging | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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PRELIMINARY
July 1999
COP8SA Family
8-Bit CMOS ROM Based and One-Time Programmable
(OTP) Microcontroller with 1k to 4k Memory, Power On
Reset, and Very Small Packaging
General Description
Note: COP8SAx devices are instruction set and pin com-
patible supersets of the COP800 Family devices, and are
replacements for these in new designs when possible.
The COPSAx Rom based and OTP microcontrollers are
highly integrated COP8™ feature core devices, with 1k to 4k
memory and advanced features including low EMI. These
single-chip CMOS devices are suited for low cost applica-
tions requiring a full featured controller, low EMI, and POR.
100% form-fit-function compatible OTP versions are avail-
able with 1k, 2k, and 4k memory, and in a variety of pack-
ages including 28-pin CSP. Erasable windowed versions are
available for use with a range of COP8 software and hard-
ware development tools.
Family features include an 8-bit memory mapped architec-
ture, 10 MHz CKI with 1 µs instruction cycle, one multi-
function 16-bit timer/counter with PWM output,
MICROWIRE/PLUS™ serial I/O, two power saving HALT/
IDLE modes, MIWU, idle timer, on-chip R/C oscillator, 12
high current outputs, user selectable options (WATCH-
DOG™, 4 clock/oscillator modes, power-on-reset), low EMI
2.7V to 5.5V operation, and 16/20/28/40/44 pin packages.
Devices included in this datasheet are:
Device
COP8SAA5
COP8SAB5
COP8SAC5
COP8SAA7
COP8SAB7
COP8SAC7
COP8SAA7SLB9
COP8SAB7SLB9
COP8SAC7SLB9
COP8SAC7-Q3
COP8SAC7-J3
Memory
(bytes)
1k ROM
2k ROM
4k ROM
1k OTP EPROM
2k OTP EPROM
4k OTP EPROM
1k OTP EPROM
2k OTP EPROM
4k OTP EPROM
4k EPROM
4k EPROM
RAM
(bytes)
64
128
128
64
128
128
64
128
128
128
128
I/O Pins
12/16/24
16/24
16/24/36/40
12/16/24
16/24
16/24
24
24
24
16/24/36
40
Packages
16/20/28 DIP/SOIC
20/28 DIP/SOIC
20/28 DIP/SOIC, 28 CSP,
40 DIP, 44 PLCC/QFP
16/20/28 DIP/SOIC
20/28 DIP/SOIC
20/28 DIP/SOIC, 28 CSP,
40 DIP, 44 PLCC/QFP
28 CSP
28 CSP
28 CSP
20/28/40 DIP
44 PLCC
Temperature
0 to +70˚C, -40 to +85˚C,
-40 to +125˚C
0 to +70˚C, -40 to +85˚C,
-40 to +125˚C
0 to +70˚C, -40 to +85˚C,
-40 to +125˚C
0 to +70˚C, -40 to +85˚C,
-40 to +125˚C
0 to +70˚C, -40 to +85˚C,
-40 to +125˚C
0 to +70˚C, -40 to +85˚C,
-40 to +125˚C
0 to +70˚C
0 to +70˚C
0 to +70˚C
Room Temp. Only
Room Temp. Only
Key Features
n Low cost 8-bit OTP microcontroller
n OTP program space with read/write protection (fully
secured)
n Quiet Design (low radiated emissions)
n Multi-Input Wakeup pins with optional interrupts
(4 to 8 pins)
n 8 bytes of user storage space in EPROM
n User selectable clock options
— Crystal/Resonator options
— Crystal/Resonator option with on-chip bias resistor
— External oscillator
— Internal R/C oscillator
n Internal Power-On Reset — user selectable
n WATCHDOG and Clock Monitor Logic — user selectable
n Up to 12 high current outputs
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
MICROWIRE/PLUS™, COP8™, MICROWIRE™ and WATCHDOG™ are trademarks of National Semiconductor Corporation.
iceMASTER® is a registered trademark of MetaLink Corporation.
© 1999 National Semiconductor Corporation DS012838
www.national.com
1 page  
Ordering Information
FIGURE 3. Part Numbering Scheme
DS012838-8
Temperature
0˚C to +70˚C
−40˚C to +85˚C
−40˚C to
+125˚C
1k EPROM
Order Number
COP8SAA716M9
COP8SAA720M9
COP8SAA728M9
COP8SAA716N9
COP8SAA720N9
COP8SAA728N9
Package
16M
20M
28M
16N
20N
28N
COP8SAA716M8
COP8SAA720M8
COP8SAA728M8
COP8SAA716N8
COP8SAA720N8
COP8SAA728N8
16M
20M
28M
16N
20N
28N
COP8SAA7SLB8
SLB
2k EPROM
Order Number Package
COP8SAB720M9
COP8SAB728M9
20M
28M
COP8SAB720N9
COP8SAB728N9
20N
28N
COP8SAB720M8
COP8SAB728M8
20M
28M
COP8SAB720N8
COP8SAB728N8
20N
28N
COP8SAB7SLB8
SLB
4k EPROM
Order Number Package
COP8SAC720M9
COP8SAC728M9
20M
28M
COP8SAC720N9
COP8SAC728N9
COP8SAC740N9
COP8SAC744V9
20N
28N
40N
44V
COP8SAC720M8
COP8SAC728M8
20M
28M
COP8SAC720N8
COP8SAC728N8
COP8SAC740N8
COP8SAC744V8
COP8SAC7SLB8
COP8SAC720M7
COP8SAC728M7
COP8SAC720N7
COP8SAC728N7
COP8SAC740N7
COP8SAC744V7
20N
28N
40N
44V
SLB
20M
28M
20N
28N
40N
44V
4k EPROM
Windowed
Device
Order Number Package
COP8SAC720Q3
COP8SAC728Q3
COP8SAC740Q3
COP8SAC744J3
20Q
28Q
40Q
44J
5 www.national.com
5 Page 
AC Electrical Characteristics (Continued)
−40˚C ≤ TA ≤ +85˚C unless otherwise specified.
Parameter
Conditions
Min Typ Max Units
Inputs
tSETUP
tHOLD
Output Propagation Delay (Note 16)
tPD1, tPD0
SO, SK
All Others
MICROWIRE Setup Time (tUWS) (Note 16)
MICROWIRE Hold Time (tUWH) (Note 16)
MICROWIRE Output Propagation Delay (tUPD)
MICROWIRE Maximum Shift Clock
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC < 4.5V
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC < 4.5V
RL = 2.2k, CL = 100 pF
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC < 4.5V
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC < 4.5V
200
500
60
150
20
56
ns
ns
ns
ns
0.7 µs
1.75
µs
1.0 µs
2.5 µs
ns
ns
220 ns
Master Mode
500 kHz
Slave Mode
1 MHz
Input Pulse Width (Note 17)
Interrupt Input High Time
Interrupt Input Low Time
Timer 1 Input High Time
Timer 1 Input Low Time
Reset Pulse Width
1 tC
1 tC
1 tC
1 tC
1 µs
Note 11: tC = Instruction cycle time (Clock input frequency divided by 10).
Note 12: Maximum rate of voltage change must be < 0.5 V/ms.
Note 13: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to VCC
and outputs driven low but not connected to a load.
Note 14: The HALT mode will stop CKI from oscillating in the R/C and the Crystal configurations. In the R/C configuration, CKI is forced high internally. In the crystal
or external configuration, CKI is TRI-STATE. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with L. F, C, G0, and G2–G5 pro-
grammed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to VCC; clock monitor disabled. Parameter refers
to HALT mode entered via setting bit 7 of the G Port data register.
Note 15: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC when
biased at voltages > VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typical). These two
pins will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes
ESD transients.
Note 16: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 17: Parameter characterized but not tested.
Note 18: Rise times faster than this specification may reset the device if POR is enabled and may affect the value of Idle Timer T0 if POR is not enabled.
DS012838-9
FIGURE 4. MICROWIRE/PLUS Timing
11
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| Páginas | Total 60 Páginas | |
| PDF Descargar | [ Datasheet COP8SA.PDF ] | |
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