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PDF COP8FGx540Nx Data sheet ( Hoja de datos )
| Número de pieza | COP8FGx540Nx | |
| Descripción | 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory/ Two Comparators and USART | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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July 1999
COP8FG Family
8-Bit CMOS ROM Based and OTP Microcontrollers with
8k to 32k Memory, Two Comparators and USART
General Description
Note: COP8FG devices are 15 MHz versions of the
COP8SG devices.
The COP8FGx5 Family ROM based microcontrollers are
highly integrated COP8™ Feature core devices with 8k to
32k memory and advanced features including Analog com-
parators, and zero external components. These single-chip
CMOS devices are suited for more complex applications re-
quiring a full featured controller with larger memory, low EMI,
two comparators, and a full-duplex USART. COP8FGx7 de-
vices are 100% form-fit-function compatible 8k or 32k OTP
(One Time Programmable) versions for use in production or
development.
Erasable windowed versions are available for use with a
range of COP8 software and hardware development tools.
Family features include an 8-bit memory mapped architec-
ture, 15 MHz CKI with 0.67 µs instruction cycle, 14 inter-
rupts, three multi-function 16-bit timer/counters with PWM,
full duplex USART, MICROWIRE/PLUS™, two analog com-
parators, two power saving HALT/IDLE modes, MIWU, idle
timer, on-chip R/C oscillator, high current outputs, user se-
lectable options (WATCHDOG™, 4 clock/oscillator modes,
power-on-reset), 4.5V to 5.5V operation, program code se-
curity, and 28/40/44 pin packages.
Devices included in this datasheet are:
Device
COP8FGE5
COP8FGG5
COP8FGH5
COP8FGK5
COP8FGR5
COP8FGE7
COP8FGR7
COP8FGR7-Q3
Memory (bytes)
8k ROM
16k ROM
20k ROM
24k ROM
32k ROM
8k OTP EPROM
32k OTP EPROM
32k EPROM
RAM
(bytes)
256
512
512
512
512
256
512
512
I/O Pins
24/36/40
24/36/40
24/36/40
24/36/40
24/36/40
24/36/40
24/36/40
24/36/40
Packages
28 DIP/SOIC, 40 DIP, 44 PLCC/QFP
28 DIP/SOIC, 40 DIP, 44 PLCC/QFP
28 DIP/SOIC, 40 DIP, 44 PLCC/QFP
28 DIP/SOIC, 40 DIP, 44 PLCC/QFP
28 DIP/SOIC, 40 DIP, 44 PLCC/QFP
28 DIP/SOIC, 40 DIP, 44 PLCC/QFP
28 DIP/SOIC, 40 DIP, 44 PLCC/QFP
28 DIP/SOIC, 40 DIP, 44 PLCC/QFP
Temperature
-40 to +85˚C
-40 to +85˚C
-40 to +85˚C
-40 to +85˚C
-40 to +85˚C
-40 to +85˚C
-40 to +85˚C
Room Temp.
Key Features
n Low cost 8-bit microcontroller
n Quiet Design (low radiated emissions)
n Multi-Input Wakeup pins with optional interrupts (8 pins)
n Mask selectable clock options
— Crystal oscillator
— Crystal oscillator option with on-chip bias resistor
— External oscillator
— Internal R/C oscillator
n Internal Power-On-Reset — user selectable
n WATCHDOG and Clock Monitor Logic — user selectable
n Eight high current outputs
n 256 or 512 bytes on-board RAM
n 8k to 32k ROM or OTP EPROM with security feature
CPU Features
n Versatile easy to use instruction set
n 0.67 µs instruction cycle time
n Fourteen multi-source vectored interrupts servicing
— External interrupt / Timers T0 — T3
— MICROWIRE/PLUS Serial Interface
— Multi-Input Wake Up
— Software Trap
— USART (2; 1 receive and 1 transmit)
— Default VIS (default interrupt)
n 8-bit Stack Pointer SP (stack in RAM)
n Two 8-bit Register Indirect Data Memory Pointers
n True bit manipulation
n BCD arithmetic instructions
Peripheral Features
n Multi-Input Wakeup Logic
n Three 16-bit timers (T1 — T3), each with two 16-bit
registers supporting:
— Processor Independent PWM mode
— External Event Counter mode
— Input Capture mode
n Idle Timer (T0)
n MICROWIRE/PLUS Serial Interface (SPI Compatible)
n Full Duplex USART
n Two Analog Comparators
COP8™, MICROWIRE/PLUS™, and WATCHDOG™ are trademarks of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
iceMASTER® is a registered trademark of MetaLink Corporation.
© 1999 National Semiconductor Corporation DS101116
www.national.com
1 page  
Connection Diagrams (Continued)
Pinouts for 28 -, 40- and 44-Pin Packages
Port
Type
Alt. Fun
28-Pin SO
L0 I/O MIWU
11
L1
I/O MIWU or CKX
12
L2
I/O MIWU or TDX
13
L3
I/O MIWU or RDX
14
L4 I/O MIWU or T2A 15
L5 I/O MIWU or T2B 16
L6 I/O MIWU or T3A 17
L7 I/O MIWU or T3B 18
G0 I/O INT
25
G1 I/O WDOUT*
26
G2 I/O T1B
27
G3 I/O T1A
28
G4 I/O SO
1
G5 I/O SK
2
G6 I SI
3
G7 I CKO
4
D0 O
19
D1 O
20
D2 O
21
D3 O
22
D4 O
29
D5 O
30
D6 O
31
D7 O
32
F0 I/O
7
F1 I/O COMP1IN−
8
F2 I/O COMP1IN+
9
F3 I/O COMP1OUT
10
F4 I/O COMP2IN−
F5 I/O COMP2IN+
F6 I/O COMP2OUT
F7 I/O
C0 I/O
C1 I/O
C2 I/O
C3 I/O
C4 I/O
C5 I/O
C6 I/O
C7 I/O
VCC
GND
6
23
CKI I
5
RESET
I
24
* G1 operation as WDOUT is controlled by ECON bit 2.
40-Pin DIP
17
18
19
20
21
22
23
24
35
36
37
38
3
4
5
6
25
26
27
28
33
34
35
36
9
10
11
12
13
14
15
16
39
40
1
2
8
33
7
34
44-Pin PLCC
17
18
19
20
25
26
27
28
39
40
41
42
3
4
5
6
29
30
31
32
27
28
29
30
9
10
11
12
13
14
15
16
43
44
1
2
21
22
23
24
8
37
7
38
44-Pin PQFP
11
12
13
14
19
20
21
22
33
34
35
36
41
42
43
44
23
24
25
26
3
4
5
6
7
8
9
10
37
38
39
40
15
16
17
18
2
31
1
32
5 www.national.com
5 Page 
4.0 Pin Descriptions
The COP8FGx I/O structure enables designers to reconfig-
ure the microcontroller’s I/O functions with a single instruc-
tion. Each individual I/O pin can be independently configured
as output pin low, output high, input with high impedance or
input with weak pull-up device. A typical example is the use
of I/O pins as the keyboard matrix input lines. The input lines
can be programmed with internal weak pull-ups so that the
input lines read logic high when the keys are all open. With
a key closure, the corresponding input line will read a logic
zero since the weak pull-up can easily be overdriven. When
the key is released, the internal weak pull-up will pull the in-
put line back to logic high. This eliminates the need for exter-
nal pull-up resistors. The high current options are available
for driving LEDs, motors and speakers. This flexibility helps
to ensure a cleaner design, with less external components
and lower costs. Below is the general description of all avail-
able pins.
VCC and GND are the power supply pins. All VCC and GND
pins must be connected.
CKI is the clock input. This can come from the Internal R/C
oscillator, external, or a crystal oscillator (in conjunction with
CKO). See Oscillator Description section.
RESET is the master reset input. See Reset description sec-
tion.
Each device contains four bidirectional 8-bit I/O ports (C, G,
L and F), where each individual bit may be independently
configured as an input (Schmitt trigger inputs on ports L and
G), output or TRI-STATE under program control. Three data
memory address locations are allocated for each of these
I/O ports. Each I/O port has two associated 8-bit memory
mapped registers, the CONFIGURATION register and the
output DATA register. A memory mapped address is also re-
served for the input pins of each I/O port. (See the memory
map for the various addresses associated with the I/O ports.)
Figure 5 shows the I/O port configurations. The DATA and
CONFIGURATION registers allow for each port bit to be in-
dividually configured under software control as shown below:
CONFIGURATION
Register
DATA
Register
Port Set-Up
0 0 Hi-Z Input
(TRI-STATE Output)
0 1 Input with Weak Pull-Up
1 0 Push-Pull Zero Output
1 1 Push-Pull One Output
Port L is an 8-bit I/O port. All L-pins have Schmitt triggers on
the inputs.
Port L supports the Multi-Input Wake Up feature on all eight
pins. Port L has the following alternate pin functions:
L7 Multi-input Wakeup or T3B (Timer T3B Input)
L6 Multi-input Wakeup or T3A (Timer T3A Input)
L5 Multi-input Wakeup or T2B (Timer T2B Input)
L4 Multi-input Wakeup or T2A (Timer T2A Input)
L3 Multi-input Wakeup and/or RDX (USART Receive)
L2 Multi-input Wakeup or TDX (USART Transmit)
L1 Multi-input Wakeup and/or CKX (USART Clock)
L0 Multi-input Wakeup
Port G is an 8-bit port. Pin G0, G2–G5 are bi-directional I/O
ports. Pin G6 is always a general purpose Hi-Z input. All pins
have Schmitt Triggers on their inputs.Pin G1 serves as the
dedicated WATCHDOG output with weak pullup if
WATCHDOG feature is selected by the Mask Option reg-
ister. The pin is a general purpose I/O if WATCHDOG fea-
ture is not selected. If WATCHDOG feature is selected, bit
1 of the Port G configuration and data register does not have
any effect on Pin G1 setup. Pin G7 is either input or output
depending on the oscillator option selected. With the crystal
oscillator option selected, G7 serves as the dedicated output
pin for the CKO clock output. With the internal R/C or the ex-
ternal oscillator option selected, G7 serves as a general pur-
pose Hi-Z input pin and is also used to bring the device out
of HALT mode with a low to high transition on G7.
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin (crystal clock option) or general purpose in-
put (R/C or external clock option), the associated bits in the
data and configuration registers for G6 and G7 are used for
special purpose functions as outlined below. Reading the G6
and G7 data bits will return zeroes.
Each device will be placed in the HALT mode by writing a “1”
to bit 7 of the Port G Data Register. Similarly the device will
be placed in the IDLE mode by writing a “1” to bit 6 of the
Port G Data Register.
Writing a “1” to bit 6 of the Port G Configuration Register en-
ables the MICROWIRE/PLUS to operate with the alternate
phase of the SK clock. The G7 configuration bit, if set high,
enables the clock start up delay after HALT when the R/C
clock configuration is used.
Config. Reg.
Data Reg.
G7 CLKDLY
HALT
G6 Alternate SK
IDLE
Port G has the following alternate features:
G7 CKO Oscillator dedicated output or general purpose in-
put
G6 SI (MICROWIRE Serial Data Input)
G5 SK (MICROWIRE Serial Clock)
G4 SO (MICROWIRE Serial Data Output)
G3 T1A (Timer T1 I/O)
G2 T1B (Timer T1 Capture Input)
G1 WDOUT WATCHDOG and/or CLock Monitor if WATCH-
DOG enabled, otherwise it is a general purpose I/O
G0 INTR (External Interrupt Input)
Port C is an 8-bit I/O port. The 40-pin device does not have
a full complement of Port C pins. The unavailable pins are
not terminated. A read operation on these unterminated pins
will return unpredictable values. The 28 pin device do not of-
fer Port C. On this device, the associated Port C Data and
Configuration registers should not be used.
Port F is an 8-bit I/O port. The 28--pin device does not have
a full complement of Port F pins. The unavailable pins are
not terminated. A read operation on these unterminated pins
will return unpredictable values.
Port F1–F3 are used for Comparator 1. Port F4–F6 are used
for Comparator 2.
The Port F has the following alternate features:
F6 COMP2OUT (Comparator 2 Output)
F5 COMP2+IN (Comparator 2 Positive Input)
F4 COMP2-IN (Comparator 2 Negative Input)
F3 COMP1OUT (Comparator 1 Output)
F2 COMP1+IN (Comparator 1 Positive Input)
F1 COMP1-IN (Comparator 1 Negative Input)
Note: For compatibility with existing software written for COP888xG devices
and with existing Mask ROM devices, a read of the Port I input pins
11 www.national.com
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| Páginas | Total 59 Páginas | |
| PDF Descargar | [ Datasheet COP8FGx540Nx.PDF ] | |
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