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PDF COP8CCE9 Data sheet ( Hoja de datos )
| Número de pieza | COP8CCE9 | |
| Descripción | 8-Bit CMOS Flash Microcontroller with 8k Memory/ Virtual EEPROM/ 10-Bit A/D and Brownout Reset | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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PRELIMINARY
April 2002
COP8CBE9/CCE9/CDE9
8-Bit CMOS Flash Microcontroller with 8k Memory,
Virtual EEPROM, 10-Bit A/D and Brownout Reset
General Description
The COP8CBE9/CCE9/CDE9 Flash microcontrollers are
highly integrated COP8™ Feature core devices, with 8k
Flash memory and advanced features including Virtual EE-
PROM, A/D, High Speed Timers, USART, and Brownout
Reset. This single-chip CMOS device is suited for applica-
tions requiring a full featured, in-system reprogrammable
controller with large memory and low EMI. The same device
is used for development, pre-production and volume produc-
tion with a range of COP8 software and hardware develop-
ment tools.
Devices included in this datasheet:
Device
Flash Program
Memory (bytes)
COP8CBE9
8k
RAM
(bytes)
256
Brownout
Voltage
2.7V to 2.9V
I/O
Pins
37,39
COP8CCE9
8k
256 4.17V to 4.5V 37,39
COP8CDE9
8k
256 No Brownout 37,39
Packages
44 LLP, 44PLCC,
48 TSSOP
44 LLP, 44PLCC,
48 TSSOP
44 LLP,
44 PLCC,
48 TSSOP
Temperature
0˚C to +70˚C
0˚C to +70˚C
−40˚C to +125˚C
0˚C to +70˚C
−40˚C to +125˚C
Features
KEY FEATURES
n 8k bytes Flash Program Memory with Security Feature
n Virtual EEPROM using Flash Program Memory
n 256byte volatile RAM
n 10-bit Successive Approximation Analog to Digital
Converter (up to 16 channels)
n 100% Precise Analog Emulation
n USART with onchip baud generator
n 2.7V – 5.5V In-System Programmability of Flash
n High endurance -100k Read/Write Cycles
n Superior Data Retention - 100 years
n Dual Clock Operation with HALT/IDLE Power Save
Modes
n Two 16-bit timers:
— Timer T2 can operate at high speed (50 ns
resolution)
— Processor Independent PWM mode
— External Event counter mode
— Input Capture mode
n Brown-out Reset (COP8CBE9/CCE9)
n High Current I/Os
— B0– B3: 10 mA @ 0.3V
— All others: 10 mA @ 1.0V
OTHER FEATURES
n Single supply operation:
— 2.7V–5.5V (0˚C to +70˚C)
— 4.5V–5.5V (−40˚C to +125˚C)
n Quiet Design (low radiated emissions)
n Multi-Input Wake-up with optional interrupts
n MICROWIRE/PLUS (Serial Peripheral Interface
Compatible)
n Clock Doubler for 20 MHz operation from 10 MHz
Oscillator, with 0.5 µs Instruction Cycle
n Eleven multi-source vectored interrupts servicing:
— External Interrupt
— USART (2)
— Idle Timer T0
— Two Timers (each with 2 interrupts)
— MICROWIRE/PLUS Serial peripheral interface
— Multi-Input Wake-up
— Software Trap
n Idle Timer with programmable interrupt interval
n 8-bit Stack Pointer SP (stack in RAM)
n Two 8-bit Register Indirect Data Memory Pointers
n True bit manipulation
n WATCHDOG and Clock Monitor logic
n Software selectable I/O options
— TRI-STATE Output/High Impedance Input
— Push-Pull Output
— Weak Pull Up Input
n Schmitt trigger inputs on I/O ports
n Temperature range: 0˚C to +70˚C and –40˚C to +125˚C
(COP8CCE9/CDE9)
n Packaging: 44 PLCC, 44 LLP and 48 TSSOP
COP8™ is a trademark of National Semiconductor Corporation.
© 2002 National Semiconductor Corporation DS200225
www.national.com
1 page  
1.0 General Description
1.1 EMI REDUCTION
The COP8CBE9/CCE9/CDE9 devices incorporate circuitry
that guards against electromagnetic interference - an in-
creasing problem in today’s microcontroller board designs.
National’s patented EMI reduction technology offers low EMI
clock circuitry, gradual turn-on output drivers (GTOs) and
internal Icc smoothing filters, to help circumvent many of the
EMI issues influencing embedded control designs. National
has achieved 15 dB–20 dB reduction in EMI transmissions
when designs have incorporated its patented EMI reducing
circuitry.
1.2 IN-SYSTEM PROGRAMMING AND VIRTUAL
EEPROM
The device includes a program in a boot ROM that provides
the capability, through the MICROWIRE/PLUS serial inter-
face, to erase, program and read the contents of the Flash
memory.
Additional routines are included in the boot ROM, which can
be called by the user program, to enable the user to custom-
ize in system software update capability if MICROWIRE/
PLUS is not desired.
Additional functions will copy blocks of data between the
RAM and the Flash Memory. These functions provide a
virtual EEPROM capability by allowing the user to emulate a
variable amount of EEPROM by initializing nonvolatile vari-
ables from the Flash Memory and occasionally restoring
these variables to the Flash Memory.
The contents of the boot ROM have been defined by Na-
tional. Execution of code from the boot ROM is dependent
on the state of the FLEX bit in the Option Register on exit
from RESET. If the FLEX bit is a zero, the Flash Memory is
assumed to be empty and execution from the boot ROM
begins. For further information on the FLEX bit, refer to
Section 4.5, Option Register.
1.3 DUAL CLOCK AND CLOCK DOUBLER
The device includes a versatile clocking system and two
oscillator circuits designed to drive a crystal or ceramic
resonator. The primary oscillator operates at high speed up
to 10 MHz. The secondary oscillator is optimized for opera-
tion at 32.768 kHz.
The user can, through specified transition sequences
(please refer to 7.0 Power Saving Features), switch execu-
tion between the high speed and low speed oscillators. The
unused oscillator can then be turned off to minimize power
dissipation. If the low speed oscillator is not used, the pins
are available as general purpose bidirectional ports.
The operation of the CPU will use a clock at twice the
frequency of the selected oscillator (up to 20 MHz for high
speed operation and 65.536 kHz for low speed operation).
This doubled clock will be referred to in this document as
‘MCLK’. The frequency of the selected oscillator will be
referred to as CKI. Instruction execution occurs at one tenth
the selected MCLK rate.
1.4 TRUE IN-SYSTEM EMULATION
On-chip emulation capability has been added which allows
the user to perform true in-system emulation using final
production boards and devices. This simplifies testing and
evaluation of software in real environmental conditions. The
user, merely by providing for a standard connector which can
be bypassed by jumpers on the final application board, can
provide for software and hardware debugging using actual
production units.
1.5 ARCHITECTURE
The COP8 family is based on a modified Harvard architec-
ture, which allows data tables to be accessed directly from
program memory. This is very important with modern
microcontroller-based applications, since program memory
is usually ROM or EPROM, while data memory is usually
RAM. Consequently constant data tables need to be con-
tained in non-volatile memory, so they are not lost when the
microcontroller is powered down. In a modified Harvard ar-
chitecture, instruction fetch and memory data transfers can
be overlapped with a two stage pipeline, which allows the
next instruction to be fetched from program memory while
the current instruction is being executed using data memory.
This is not possible with a Von Neumann single-address bus
architecture.
The COP8 family supports a software stack scheme that
allows the user to incorporate many subroutine calls. This
capability is important when using High Level Languages.
With a hardware stack, the user is limited to a small fixed
number of stack levels.
1.6 INSTRUCTION SET
In today’s 8-bit microcontroller application arena cost/
performance, flexibility and time to market are several of the
key issues that system designers face in attempting to build
well-engineered products that compete in the marketplace.
Many of these issues can be addressed through the manner
in which a microcontroller’s instruction set handles process-
ing tasks. And that’s why the COP8 family offers a unique
and code-efficient instruction set - one that provides the
flexibility, functionality, reduced costs and faster time to mar-
ket that today’s microcontroller based products require.
Code efficiency is important because it enables designers to
pack more on-chip functionality into less program memory
space (ROM, OTP or Flash). Selecting a microcontroller with
less program memory size translates into lower system
costs, and the added security of knowing that more code can
be packed into the available program memory space.
1.6.1 Key Instruction Set Features
The COP8 family incorporates a unique combination of in-
struction set features, which provide designers with optimum
code efficiency and program memory utilization.
1.6.2 Single Byte/Single Cycle Code Execution
The efficiency is due to the fact that the majority of instruc-
tions are of the single byte variety, resulting in minimum
program space. Because compact code does not occupy a
substantial amount of program memory space, designers
can integrate additional features and functionality into the
microcontroller program memory space. Also, the majority
instructions executed by the device are single cycle, result-
ing in minimum program execution time. In fact, 77% of the
instructions are single byte single cycle, providing greater
code and I/O efficiency, and faster code execution.
1.6.3 Many Single-Byte, Multi-Function Instructions
The COP8 instruction set utilizes many single-byte, multi-
function instructions. This enables a single instruction to
accomplish multiple functions, such as DRSZ, DCOR, JID,
LD (Load) and X (Exchange) instructions with post-
incrementing and post-decrementing, to name just a few
5 www.national.com
5 Page 
DC Electrical Characteristics (−40˚C ≤ TA ≤ +125˚C) (Continued)
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Parameter
Conditions
Min Typ
RAM Retention Voltage, VR (in HALT Mode)
Input Capacitance
2.0
Voltage on G6 to Force Execution from Boot
ROM(Note 8)
G6 rise time must be slower
than 100 ns
2 x VCC
G6 Rise Time to Force Execution from Boot ROM
Input Current on G6 when Input > VCC
VIN = 11V, VCC = 5.5V
100
500
Max
7
VCC + 7
Units
V
pF
V
nS
µA
AC Electrical Characteristics (−40˚C ≤ TA ≤ +125˚C)
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Parameter
Conditions
Min Typ Max
Units
Instruction Cycle Time (tC)
Crystal/Resonator
Output Propagation Delay
Frequency of MICROWIRE/PLUS in Slave
Mode
4.5V ≤ VCC ≤ 5.5V
RL =2.2k, CL = 100 pF
0.5
DC µs
2 MHz
MICROWIRE/PLUS Setup Time (tUWS)
MICROWIRE/PLUS Hold Time (tUWH)
MICROWIRE/PLUS Output Propagation Delay
(tUPD)
Input Pulse Width
20 ns
20 ns
150 ns
Interrupt Input High Time
Interrupt Input Low Time
Timer 1 Input High Time
Timer 1 Input Low Time
Timer 2, 3 Input High Time (Note 6)
Timer 2, 3 Input Low Time (Note 6)
Output Pulse Width
1 tC
1 tC
1 tC
1 tC
1 MCLK or tC
1 MCLK or tC
Timer 2, 3 Output High Time
150 ns
Timer 2, 3 Output Low Time
150 ns
USART Bit Time when using External CKX
6 CKI
periods
USART CKX Frequency when being Driven by
Internal Baud Rate Generator
2 MHz
Reset Pulse Width
tC = instruction cycle time.
Note 10: Maximum rate of voltage change must be < 0.5 V/ms.
0.5
tC
Note 11: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to VCC
and outputs driven low but not connected to a load.
Note 12: The HALT mode will stop CKI from oscillating. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with L. A. B, C, E, F,
G0, and G2–G5 programmed as low outputs and not driving a load; all D outputs programmed low and not driving a load; all inputs tied to VCC; A/D converter and
clock monitor and BOR disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register.
Note 13: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC
when biased at voltages > VCC (the pins do not have source current when biased at a voltage below VCC). These two pins will not latch up. The voltage at the pins
must be limited to < (VCC + 7V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD transients.
Note 14: If timer is in high speed mode, the minimum time is 1 MCLK. If timer is not in high speed mode, the minimum time is 1 tC.
Note 15: Absolute Maximum Ratings should not be exceeded.
Note 16: Vcc must be valid and stable before G6 is raised to a high voltage.
11 www.national.com
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet COP8CCE9.PDF ] | |
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