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PDF COP8ACC728N8-XE Data sheet ( Hoja de datos )
| Número de pieza | COP8ACC728N8-XE | |
| Descripción | 8-Bit CMOS OTP Microcontroller with 16k Memory and High Resolution A/D | |
| Fabricantes | National Semiconductor | |
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May 1999
COP8ACC7
8-Bit CMOS OTP Microcontroller with 16k Memory and
High Resolution A/D
General Description
The COP8ACC7 OTP (One Time Programmable) microcon-
trollers are highly integrated COP8™ Feature core devices
with 16k memory and advanced features including a High-
Resolution A/D. This multi-chip CMOS device is suited for
applications requiring a full featured controller with a high
resolution A/D (only one external capacitor required), and for
pre-production devices for a ROM design. Pin and software
compatible (different VCC range) 4k ROM versions are avail-
able (COPACC5). Erasable windowed versions are available
for use with a range of COP8 software and hardware devel-
opment tools.
Family features include an 8-bit memory mapped architec-
ture, 4 MHz CKI with 2.5 µs instruction cycle, two external
clock options (–XE = Crystal; –RE = RC), 6 channel A/D with
12-bit resolution, analog capture timer, analog current
source and VCC/2 reference, one multi-function 16-bit timer/
counter, MICROWIRE/PLUS™ serial I/O, two power saving
HALT/IDLE modes, MIWU, high current outputs, software
selectable I/O options, WATCHDOG™ timer and Clock Moni-
tor, 2.7V to 5.5V operation, program code security, and
20/28 pin packages.
Device included in this datasheet is:
Device
COP8ACC7xxx9
COP8ACC7xxx8
Memory (bytes)
16k OTP EPROM
16k OTP EPROM
RAM (bytes)
128
128
I/O Pins
15/23
15/23
Packages
20 SOIC, 28 DIP/SOIC
20 SOIC, 28 DIP/SOIC
Temperature
0 to +70˚C
-40 to +85˚C
Key Features
n Analog Function Block with 12-bit A/D including:
— Analog comparator with seven input muxes
— Constant Current Source and VCC/2 Reference
— 16-bit capture timer (upcounter) clocked from CKI
with auto reset on timer startup
n Quiet design (reduced radiated emissions)
n 4096 bytes on-board OTP EPROM with security feature
n 128 bytes on-board RAM
Additional Peripheral Features
n Idle Timer
n One 16-bit timer with two 16-bit registers supporting:
— Processor Independent PWM mode
— External Event counter mode
— Input Capture mode
n Multi-Input Wake-Up (MIWU) with optional interrupts
n WATCHDOG and clock monitor logic
n MICROWIRE/PLUS serial I/O with programmable shift
clock-polarity
I/O Features
n Software selectable I/O options (Push-Pull Output, Weak
Pull-Up Input, High Impedance Input)
n High current outputs
n Schmitt Trigger inputs on ports G and L
n Packages:
— 28 DIP/SO with 23 I/O pins
— 20 SO with 15 I/O pins
CPU/Instruction Set Features
n 2.5 µs instruction cycle time
n Eight multi-source vectored interrupt servicing:
— External Interrupt
— Idle Timer T0
— Timer T1 associated Interrupts
— MICROWIRE/PLUS
— Multi-Input Wake Up
— Software Trap
— Default VIS
— A/D (Capture Timer)
n 8-bit Stack Pointer (SP) — stack in RAM
n Two 8-bit Registers Indirect Data Memory Pointers
(B and X)
Fully Static CMOS
n Two power saving modes: HALT and IDLE
n Temperature ranges: 0˚C to +70˚C, −40˚C to +85˚C
n Available with Crystal (-XE) or R/C (-RE) oscillator
Development System
n Emulation device for COP8ACC5
n Real time emulation and full program debug offered by
MetaLink® development system
Applications
n Battery Chargers
n Appliances
n Data Acquisition systems
Driveway™ is a trademark of Aisys Intelligent Systems.
COP8™, MICROWIRE™, MICROWIRE/PLUS™, and WATCHDOG™ are trademarks of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
iceMASTER® is a registered trademark of MetaLink Corporation.
© 1999 National Semiconductor Corporation DS012869
www.national.com
1 page  
DC Electrical Characteristics (Continued)
0˚C ≤ TA ≤ +70˚C unless otherwise specified
Parameter
Input Capacitance
(Note 6)
Load Capacitance on D2
(Note 6)
Conditions
Min Typ
Max
Units
7 pF
1000
pF
AC Electrical Characteristics
0˚C ≤ TA ≤ +70˚C unless otherwise specified
Parameter
Conditions
Min Typ
Max
Units
Instruction Cycle Time (Note 8)
Crystal, Resonator
R/C Oscillator
Inputs
2.7V ≤ VCC ≤ 4V
4V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 4V
4V ≤ VCC ≤ 5.5V
2.5
1.0
7.5
3.0
DC µs
DC µs
DC µs
DC µs
tSETUP
tHOLD
Output Propagation Delay (Note 6)
tPD1, tPD0
SO, SK
All Others
MICROWIRE™ Setup Time (tUWS) (Note 6)
MICROWIRE Hold Time (tUWH) (Note 6)
MICROWIRE Output Propagation Delay (tUPD)
Input Pulse Width (Note 7)
4V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 4V
4V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 4V
RL = 2.2k, CL = 100 pF
4V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 4V
4V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 4V
VCC ≥ 4V
VCC ≥ 4V
VCC ≥ 4V
200
500
60
150
20
56
ns
ns
ns
ns
0.7 µs
1.75
µs
1 µs
2.5 µs
ns
ns
220 ns
Interrupt Input High Time
Interrupt Input Low Time
Timer 1, 2, 3 Input High Time
Timer 1, 2, 3 Input Low Time
Reset Pulse Width
1 tC
1 tC
1 tC
1 tC
1 µs
Note 2: Maximum rate of voltage change must be < 0.5V/ms.
Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 4: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Measurement of IDD HALT is done with device neither sourcing or
sinking current; with L, C, and G0–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to VCC;
clock monitor and comparator disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up CKI during HALT in crystal
clock mode.
Note 5: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC when
biased at voltages > VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typical). These two
pins will not latch up. The voltage at the pins must be limited to less than 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning
excludes ESD transients.
Note 6: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 7: Parameter characterized but not tested.
Note 8: tC = Instruction Cycle Time.
5 www.national.com
5 Page 
Pin Descriptions (Continued)
Configuration Data
Register
Register
Port Set-Up
0 0 Hi-Z Input (TRI-STATE Output)
0 1 Input with Weak Pull-Up
1 0 Push-Pull Zero Output
1 1 Push-Pull One Output
Please note:
The lower 4 L-bits read all ones (L0:L3). This is independant
from the states of the associated bits in the L-port Data- and
Configuration register. The lower 4 bits in the L-port Data-
and Configuration register can be used as general purpose
status indicators (flags).
Port G is an 8-bit port with 5 I/O pins (G0, G2–G5), an input
pin (G6), and a dedicated output pin (G7). Pins G0 and
G2–G6 all have Schmitt Triggers on their inputs. Pin G1
serves as the dedicated WDOUT WATCHDOG output, while
pin G7 is either input or output depending on the oscillator
mask option selected. With the crystal oscillator option se-
lected, G7 serves as the dedicated output pin for the CKO
clock output. With the single-pin R/C oscillator mask option
selected, G7 serves as a general purpose input pin but is
also used to bring the device out of HALT mode with a low to
high transition on G7. There are two registers associated
with the G Port, a data register and a configuration register.
Therefore, each of the 5 I/O bits (G0, G2–G5) can be indi-
vidually configured under software control.
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin (crystal clock option) or general purpose in-
put (R/C clock option), the associated bits in the data and
configuration registers for G6 and G7 are used for special
purpose functions as outlined below. Reading the G6 and G7
data bits will return zeros.
Note that the chip will be placed in the HALT mode by writing
a “1” to bit 7 of the Port G Data Register. Similarly the chip
will be placed in the IDLE mode by writing a “1” to bit 6 of the
Port G Data Register.
Writing a “1” to bit 6 of the Port G Configuration Register en-
ables the MICROWIRE/PLUS to operate with the alternate
phase of the SK clock. The G7 configuration bit, if set high,
enables the clock start up delay after HALT when the R/C
clock configuration is used.
Config Reg.
Data Reg.
G7 CLKDLY
HALT
G6 Alternate SK
IDLE
Port G has the following alternate features:
G6 SI (MICROWIRE Serial Data Input)
G5 SK (MICROWIRE Serial Clock)
G4 SO (MICROWIRE Serial Data Output)
G3 T1A (Timer T1 I/O)
G2 T1B (Timer T1 Capture Input)
G0 INTR (External Interrupt Input)
Port G has the following dedicated functions:
G7 CKO Oscillator dedicated output or general purpose
input
G1 WDOUT WATCHDOG and/or Clock Monitor dedicated
output.
Port I is an eight-bit Hi-Z input port.
Port I0–I7 are used for the analog function block.
The Port I has the following alternate features:
I7 COUT (Comparator Output)
I6 Analog CH6 (Comparator Positive Input 6)
I5 Analog CH5 (Comparator Positive Input 5)
I4 Analog CH4 (Comparator Positive Input 4)
I3 Analog CH3 (Comparator Positive Input 3/Comparator
Output)
I2 Analog CH2 (Comparator Positive Input 2)
I1 ISRC (Comparator Negative Input/Current Source Out)
I0 Analog CH1 (Comparator Positive Input 1)
Port D is a 4-bit output port that is preset high when RESET
goes low. The user can tie two or more D port outputs (ex-
cept D2) together in order to get a higher drive.
Functional Description
The architecture of the device is a modified Harvard archi-
tecture. With the Harvard architecture, the control store pro-
gram memory (ROM) is separated from the data store
memory (RAM). Both ROM and RAM have their own sepa-
rate addressing space with separate address buses. The ar-
chitecture, though based on the Harvard architecture, per-
mits transfer of data from ROM to RAM.
CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or shift
operation in one instruction (tC) cycle time.
There are six CPU registers:
A is the 8-bit Accumulator Register
PC® is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). The SP is initialized to RAM ad-
dress 06F with reset.
All the CPU registers are memory mapped with the excep-
tion of the Accumulator (A) and the Program Counter (PC).
PROGRAM MEMORY
The program memory consists of 16,384 bytes of OTP
EPROM. These bytes may hold program instructions or con-
stant data (data tables for the LAID instruction, jump vectors
for the JID instruction, and interrupt vectors for the VIS in-
struction). The program memory is addressed by the 15-bit
program counter (PC). All interrupts in the device vector to
program memory location 0FF Hex.
The device can be configured to inhibit external reads of the
program memory. This is done by programming the Security
Byte.
SECURITY FEATURE
The program memory array has an associate Security Byte
that is located outside of the program address range. This
byte can be addressed only from programming mode by a
programmer tool.
Security is an optional feature and can only be asserted after
the memory array has been programmed and verified. A se-
cured part will read all 00(hex) by a programmer. The part
11 www.national.com
11 Page | ||
| Páginas | Total 40 Páginas | |
| PDF Descargar | [ Datasheet COP8ACC728N8-XE.PDF ] | |
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