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COP888EK の電気的特性と機能

COP888EKのメーカーはNational Semiconductorです、この部品の機能は「8-Bit CMOS ROM Based Microcontrollers with 8k Memory/ Comparator/ and Single-slope A/D Capability」です。


製品の詳細 ( Datasheet PDF )

部品番号 COP888EK
部品説明 8-Bit CMOS ROM Based Microcontrollers with 8k Memory/ Comparator/ and Single-slope A/D Capability
メーカ National Semiconductor
ロゴ National Semiconductor ロゴ 




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COP888EK Datasheet, COP888EK PDF,ピン配置, 機能
OBSOLETE
January 2000
COP888EK
8-Bit CMOS ROM Based Microcontrollers with 8k
Memory, Comparator, and Single-slope A/D Capability
General Description
The COP888EK ROM based microcontrollers are highly in-
tegrated COP8Feature core devices with 8k memory and
advanced features including a Multi-Input Comparator and
Single-slope A/D capability. These single-chip CMOS de-
vices are suited for applications requiring a full featured, low
EMI controller with an analog comparator, current source,
and voltage reference. The COP87L88EK/RK Family de-
vices are pin and software compatible (different VCC range)
16k or 32k OTP (One Time Programmable) versions for pre-
production, and for use with a range of COP8 software and
hardware development tools.
Family features include an 8-bit memory mapped architec-
ture, 10 MHz CKI with 1µs instruction cycle, three multi-
function 16-bit timer/counters with PWM, MICROWIRE/
PLUSserial I/O, one analog comparator with seven input
multiplexor, an analog current source and VCC reference,
two power saving HALT/IDLE modes, idle timer, MIWU, high
current outputs, software selectable I/O options, WATCH-
DOGtimer and Clock Monitor, Low EMI 2.5V to 6.0V op-
eration and 28/40/44 pin packages.
Devices included in this datasheet are:
Device Memory (bytes) RAM (bytes) I/O Pins Packages Temperature
Comments
COP684EK
8k ROM
256
24 28 DIP/SOIC
-55 to +125˚C 4.5V - 5.5V
COP884EK
8k ROM
256
24 28 DIP/SOIC
-40 to +85˚C
COP984EK
8k ROM
256
24 28 DIP/SOIC
0 to +70˚C 2.5V - 4.0V, EKH=4.0V - 6.0V
COP688EK
8k ROM
256 36/40 40 DIP, 44 PLCC -55 to +125˚C 4.5V - 5.5V
COP888EK
8k ROM
256 36/40 40 DIP, 44 PLCC -40 to +85˚C
COP988EK
8k ROM
256 36/40 40 DIP, 44 PLCC 0 to +70˚C 2.5V - 4.0V, EKH=4.0V - 6.0V
Key Features
n Analog function block with
— Analog comparator with seven input multiplexor
— Constant current source and VCC/2 reference
n Three 16-bit timers, each with two 16-bit registers
supporting:
— Processor Independent PWM mode
— External Event counter mode
— Input Capture mode
n 8 kbytes of on-chip ROM
n 256 bytes of on-chip RAM
Additional Peripheral Features
n Idle Timer
n Multi-Input Wake Up (MIWU) with optional interrupts (8)
n WATCHDOG and Clock Monitor logic
n MICROWIRE/PLUS serial I/O
I/O Features
n Software selectable I/O options (TRI-STATEOutput,
Push-Pull Output, Weak Pull-Up Input, High Impedance
Input)
n High current outputs
n Schmitt trigger inputs on Port G and L
n Packages: 44 PLCC with 40 I/O pins, 40 DIP with 36 I/O
pins, and 28 DIP/SO with 24 I/O pins
CPU/Instruction Set Feature
n 1 µs instruction cycle time
n Twelve multi-source vectored interrupts servicing
— External Interrupt with selectable edge
— Idle Timer T0
— Three Timers (Each with 2 interrupts)
— MICROWIRE/PLUS
— Multi-Input Wake Up
— Software Trap
— Default VIS (default interrupt)
n Versatile and easy to use instruction set
n 8-bit Stack Pointer (SP) — stack in RAM
n Two 8-bit Register Indirect Data Memory Pointers
(B, X)
Fully Static CMOS
n Single supply operation: 2.5V to 6.0V
n Temperature ranges: 0˚C to +70˚C, −40˚C to +85˚C, and
−55˚C to +125˚C
COP8, MICROWIRE/PLUS, and WATCHDOGare trademarks of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
iceMASTER® is a registered trademark of MetaLink Corporation.
© 2000 National Semiconductor Corporation DS012094
www.national.com

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COP888EK pdf, ピン配列
Connection Diagrams
Plastic Chip Carrier
Dual-In-Line Package
DS012094-2
Top View
Order Number COP688EK-XXX/V, COP888EK-XXX/V,
COP988EK-XXX/V or COP988EKH-XXX/V
See NS Plastic Chip Package Number V44A
DS012094-3
Top View
Order Number COP688EK-XXX/N, COP888EK-XXX/N,
COP988EK-XXX/N or COP988EKH-XXX/N
See NS Molded Package Number N40A
Dual-In-Line Package
DS012094-4
Top View
Order Number COP684EK-XXX/N, COP884EK-XXX/N, COP984EK-XXX/N or COP984EKH-XXX/N
See NS Molded Package Number N28B
Order Number COP684EK-XXX/WM, COP884EK-XXX/WM, COP984EK-XXX/WM or COP984EKH-XXX/WM
See NS Molded Package Number M28B
FIGURE 2. Connection Diagrams
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3Pages


COP888EK 電子部品, 半導体
DC Electrical Characteristics 98xEK: (Continued)
0˚C TA + 70˚C unless otherwise specified
Parameter
Input Capacitance
Load Capacitance on D2
Conditions
Min Typ
Max
7
1000
Units
pF
pF
AC Electrical Characteristics 98xEK:
0˚C TA+ 70˚C unless otherwise specified
Parameter
Conditions
Min Typ Max Units
Instruction Cycle Time (tc)
Crystal, Resonator,
R/C Oscillator
Inputs
tSETUP
tHOLD
Output Propagation Delay (Note 7)
tPD1, tPD0
SO, SK
All Others
MICROWIRESetup Time (tUWS) (Note 7)
MICROWIRE Hold Time (tUWH) (Note 7)
MICROWIRE Output Propagation Delay (tUPD)
Input Pulse Width (Note 8)
4.0V VCC 6.0V
2.5V VCC < 4.0V
4.0V VCC 6.0V
2.5V VCC < 4.0V
4.0V VCC 6.0V
2.5V VCC < 4.0V
4.0V VCC 6.0V
2.5V VCC < 4.0V
RL = 2.2k, CL = 100 pF
4.0V VCC 6.0V
2.5V VCC < 4.0V
4.0V VCC 6.0V
2.5V VCC < 4.0V
VCC 4.0V
VCC 4.0V
VCC 4.0V
1.0
2.5
3.0
7.5
200
500
60
150
20
56
DC
DC
DC
DC
0.7
1.75
1
2.5
220
µs
µs
µs
µs
ns
ns
ns
ns
µs
µs
µs
µs
ns
ns
ns
Interrupt Input High Time
Interrupt Input Low Time
Timer 1, 2, 3 Input High Time
Timer 1, 2, 3 Input Low Time
Reset Pulse Width
1.0 tc
1.0 tc
1.0 tc
1.0 tc
1.0 µs
Note 2: tc = Instruction Cycle Time
Note 3: Maximum rate of voltage change must be < 0.5 V/ms.
Note 4: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to VCC
and outputs driven low but not connected to a load.
Note 5: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Measurement of IDD HALT is done with device neither sourcing nor
sinking current; with L, C, and G0–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to VCC;
clock monitor and comparator disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up CKI during HALT in crystal
clock mode.
Note 6: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC when
biased at voltages > VCC(the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750(typical). These two
pins will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning ex-
cludes ESD transients.
Note 7: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 8: Parameter characterized but not tested.
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共有リンク

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