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PDF COP888CF Data sheet ( Hoja de datos )
| Número de pieza | COP888CF | |
| Descripción | 8-Bit CMOS ROM Based Microcontrollers with 4k Memory and A/D Converter | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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September 1999
COP884BC/COP885BC
8-Bit CMOS ROM Based Microcontrollers with 2k
Memory, Comparators, and CAN Interface
General Description
The COP884BC ROM based microcontrollers are highly in-
tegrated COP8™ Feature core devices with 2k memory and
advanced features including a CAN 2.0B (passive) interface
and two Analog comparators. These single-chip CMOS de-
vices are suited for applications requiring a full featured con-
troller with a CAN interface, low EMI, and an 8-bit 39 kHz
PWM timer. COP87L84BC devices are pin and software
compatible 16k OTP (One Time Programmable) versions for
pre-production, and for use with a range of COP8 software
and hardware development tools.
Features include an 8-bit memory mapped architecture, 10
MHz CKI (crystal osc) with 1µs instruction cycle, one multi-
function 16-bit timer/counter, 8-bit 39 kHz PWM timer with 2
outputs, CAN 2.0B (passive) interface, MICROWIRE/
PLUS™ serial I/O, two Analog comparators, two power sav-
ing HALT/IDLE modes, idle timer, MIWU, software selectable
I/O options, Power on Reset, low EMI 4.5V to 5.5V opera-
tion, and 20/28 pin packages.
Note: A companion device with CAN interface, more I/O and
memory, A/D, and USART is the COP888EB.
Devices included in this datasheet are:
Device
COP684BC
COP884BC
COP685BC
COP885BC
Memory (bytes)
2k ROM
2k ROM
2k ROM
2k ROM
RAM (bytes)
64
64
64
64
I/O Pins
18
18
10
10
Packages
28 SOIC
28 SOIC
20 SOIC
20 SOIC
Temperature
-55 to +125˚C
-40 to +85˚C
-55 to +125˚C
-40 to +85˚C
Key Features
n CAN 2.0B (passive) Interface
n Power On Reset (selectable)
n One 16-bit timer, with two 16-bit registers supporting:
— Processor Independent PWM mode
— External Event counter mode
— Input Capture mode
n High speed, constant resolution 8-bit PWM/frequency
monitor timer with 2 output pins
n 2048 bytes on-board ROM
n 64 bytes on-board RAM
Additional Peripheral Features
n Idle Timer
n Multi-Input Wake Up (MIWU) with optional interrupts (7)
n Two analog comparators
n MICROWIRE/PLUS serial I/O
I/O Features
n Memory mapped I/O
n Software selectable I/O options (TRI-STATE® Output,
Push-Pull Output, Weak Pull-Up Input, High Impedance
Input)
n Schmitt trigger inputs on ports G and L
n Packages: 28 SO with 18 I/O pins and 20 SO with 10
I/O pins
CPU/Instruction Set Features
n 1 µs instruction cycle time
n Eleven multi-source vectored interrupts servicing
— External Interrupt
— Idle Timer T0
— Timer T1 (with 2 Interrupts)
— MICROWIRE/PLUS
— Multi-Input Wake Up
— Software Trap
— PWM Timer
— CAN Interface (with 3 interrupts)
n Versatile and easy to use instruction set
n 8-bit Stack Pointer (SP) — stack in RAM
n Two 8-bit Register Indirect Data Memory Pointers
(B and X)
Fully Static CMOS
n Two power saving modes: HALT and IDLE
n Low current drain (typically <1 µA)
n Single supply operation: 4.5V–5.5V
n Temperature ranges: −40˚C to +85˚C, −55˚C to +125˚C
Development Support
n Emulation and OTP devices
n Real time emulation and full program debug offered by
MetaLink Development Systems
COP8™, and MICROWIRE/PLUS™ are trademarks of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
iceMASTER® is a registered trademark of MetaLink Corporation.
© 1999 National Semiconductor Corporation DS012067
www.national.com
1 page  
DC Electrical Characteristics COP884BC: (Continued)
−40˚C ≤ TA ≤ +85˚C
Parameter
Maximum Input Current
without Latchup (Notes 8, 10)
RAM Retention Voltage, Vr (Note 9)
Input Capacitance
Load Capacitance on D2
Conditions
Room Temp
500 ns Rise and Fall Time
(Note 10)
Min
Typ
Max
Units
±100
mA
2.0 V
7 pF
1000
pF
Note 3: Maximum rate of voltage change must be less than 0.5 V/ms
Note 4: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at VCC or GND, and outputs open.
Note 5: The HALT mode will stop CKI from oscillating in the Crystal configurations. Halt test conditions: All inputs tied to VCC; L, and G port I/Os configured as outputs
and programmed low; D outputs programmed low. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up CKI during
HALT in crystal clock mode.
Note 6: HALT and IDLE current specifications assume CAN block and comparators are disabled.
5 www.national.com
5 Page 
Pin Descriptions (Continued)
isters associated with the G Port, a data register and a con-
figuration register. Therefore, each of the 6 I/O bits (G0–G5)
can be individually configured under software control.
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin the associated bits in the data and configu-
ration registers for G6 and G7 are used for special purpose
functions as outlined below. Reading the G6 and G7 data
bits will return zeroes.
Note that the chip will be placed in the HALT mode by writing
a “1” to bit 7 of the Port G Data Register. Similarly the chip
will be placed in the IDLE mode by writing a “1” to bit 6 of the
Port G Data Register.
Writing a “1” to bit 6 of the Port G Configuration Register en-
ables the MICROWIRE/PLUS to operate with the alternate
phase of the SK clock.
Config. Register
Data Register
G7 HALT
G6 Alternate SK
IDLE
CAN pins: For the on-chip CAN interface this device has five
dedicated pins with the following features:
VREF On-chip reference voltage with the value of VCC/2
Rx0 CAN receive data input pin.
Rx1 CAN receive data input pin.
Tx0 CAN transmit data output pin. This pin may be put in
the TRI-STATE mode with the TXEN0 bit in the CAN
Bus control register.
Tx1 CAN transmit data output pin. This pin may be put in
the TRI-STATE mode with the TXEN1 bit in the CAN
Bus control register.
Port G has the following alternate features:
G6 SI (MICROWIRE Serial Data Input)
G5 SK (MICROWIRE Serial Clock)
G4 SO (MICROWIRE Serial Data Output)
G3 T1A (Timer T1 I/O)
G2 T1B (Timer T1 Capture Input)
G0 INTR (External Interrupt Input)
Port G has the following dedicated function:
G7 CKO Oscillator dedicated output
Port D is a 4-bit output port that is preset high when RESET
goes low. The user can tie two or more D port outputs (ex-
cept D2) together in order to get a higher drive.
Note: Care must be exercised with the D2 pin operation. At RESET, the ex-
ternal loads on this pin must ensure that the output voltages stay
above 0.8 VCC to prevent the chip from entering special modes. Also
keep the external loading on D2 to less than 1000 pF.
FIGURE 5. I/O Port Configurations
DS012067-5
Functional Description
The architecture of the device utilizes a modified Harvard ar-
chitecture. With the Harvard architecture, the control store
program memory (ROM) is separated from the data store
memory (RAM). Both ROM and RAM have their own sepa-
rate addressing space with separate address buses. The ar-
chitecture, though based on Harvard architecture, permits
transfer of data from ROM to RAM.
CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or shift
operation in one instruction (tc) cycle time.
There are five CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). The SP is initialized to RAM ad-
dress 02F with reset.
All the CPU registers are memory mapped with the excep-
tion of the Accumulator (A) and the Program Counter (PC).
PROGRAM MEMORY
Program memory for the device consists of 2048 bytes of
ROM. These bytes may hold program instructions or con-
stant data (data tables tor the LAID instruction, jump vectors
for the JID instruction, and interrupt vectors for the VIS in-
struction). The program memory is addressed by the 15-bit
program counter (PC). All interrupts in the device vector to
program memory location 0FF Hex.
DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data and
Pin), the control registers, the MICROWIRE/PLUS SIO shift
register, and the various registers, and counters associated
with the timers (with the exception of the IDLE timer). Data
memory is addressed directly by the instruction or indirectly
by the B, X and SP pointers.
11 www.national.com
11 Page | ||
| Páginas | Total 57 Páginas | |
| PDF Descargar | [ Datasheet COP888CF.PDF ] | |
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