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PDF AD8284 Data sheet ( Hoja de datos )
| Número de pieza | AD8284 | |
| Descripción | 4-Channel Mux | |
| Fabricantes | Analog Devices | |
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Data Sheet
Radar Receive Path AFE: 4-Channel Mux
with LNA, PGA, AAF, and ADC
AD8284
FEATURES
4-channel mux to LNA, PGA, AAF
1 direct-to-ADC channel
Programmable gain amplifier (PGA)
Includes low noise preamplifier (LNA)
SPI-programmable gain = 17 dB to 35 dB in 6 dB steps
Antialiasing filter (AAF)
Programmable third-order low-pass elliptic filter (LPF) from
9 MHz to 15 MHz
Analog-to-digital converter (ADC)
12 bits of accuracy of up to 60 MSPS
SNR = 67 dB
SFDR = 68 dBc
Low power, 345 mW at 12 bits per 60 MSPS
Low noise, 3.5 nV/√Hz maximum of input referred
voltage noise
Power-down mode
64-lead, 10 mm × 10 mm TQFP package
Specified from −40°C to +105°C
Qualified for automotive applications
APPLICATIONS
Automotive radar
Adaptive cruise control
Collision avoidance
Blind spot detection
Self parking
Electronic bumper
GENERAL DESCRIPTION
The AD8284 is an integrated analog front end designed for low
cost, compact size, flexibility, and ease of use. It contains a
4-channel differential multiplexer (mux), a 1-channel low noise
preamplifier (LNA) with a programmable gain amplifier (PGA)
and an antialiasing filter (AAF), as well as one direct-to-ADC
channel, all integrated with a single, 12-bit analog-to-digital
converter (ADC). The AD8284 also incorporates a saturation
detection circuit for high frequency overvoltage conditions that
would otherwise be filtered by the AAF.
The analog channel features a gain range of 17 dB to 35 dB in
6 dB increments, and an ADC with a conversion rate of up to
60 MSPS. The combined input referred voltage noise of the entire
channel is 3.5 nV/√Hz at maximum gain. The channel is optimized
FUNCTIONAL BLOCK DIAGRAM
INA+
INA–
INB+
INB–
INC+
INC–
IND+
IND–
INADC+
INADC–
SATURATION
DETECTION
REFERENCE
AD8284
MUX LNA
PGA
AAF
MUX
12-BIT
ADC
D0
TO
D11
SPI
Figure 1.
for dynamic performance and low power in applications where
a small package size is critical.
Fabricated in an advanced CMOS process, the AD8284 is available
in a 10 mm × 10 mm, RoHS compliant, 64-lead TQFP. It is speci-
fied over the automotive temperature range of −40°C to +105°C.
Table 1. Related Devices
Part No. Description
AD8285 4-Channel LNA/PGA/AAF, pseudosimultaneous
channel sampling with ADC
AD8283 6-Channel LNA/PGA/AAF, pseudosimultaneous
channel sampling with ADC
ADA8282 4-Channel LNA/PGA
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD8284
DIGITAL SPECIFICATIONS
AVDD18x = 1.8 V, AVDD33x = 3.3 V, DVDD18x = 1.8 V, DVDD33x = 3.3 V, 1.00 V internal ADC reference, fIN = 2.5 MHz, fS = 60 MSPS,
RS = 50 Ω, LNA + PGA gain = 35 dB, LPF cutoff = fSAMPLECH/4, 12-bit operation, temperature = −40°C to +105°C, all specifications
guaranteed by testing, unless otherwise noted.
Table 3.
Parameter1
CLOCK INPUTS (CLK+, CLK−)2
Logic Compliance
Differential Input Voltage3
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS (PDWN, SCLK, AUX, MUX[0], MUX[1], ZSEL)2
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (CS)2
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (SDI)2
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUT (SDO)
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
LOGIC OUTPUTS (D11 to D0, SFLAG)
Logic 1 Voltage (IOH = 2 mA)
Logic 0 Voltage (IOL = 2 mA)
Temperature
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
Full
Full
Min Typ Max
CMOS/LVDS/LVPECL
250
1.2
20
1.5
1.2 3.6
0.3
30
0.5
1.2 3.6
0.3
70
0.5
1.2 DVDD33x + 0.3
0 0.3
30
2
3.0
0.3
3.0
0.3
Unit
mV p-p
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
V
V
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and testing methodology.
2 Guaranteed by design only.
3 Specified for LVDS and LVPECL only.
Rev. D | Page 5 of 28
5 Page 
Data Sheet
1,000,000
100,000
10,000
1,000
100
10
1
0.01
0.1 1 10
FREQUENCY (MHz)
100
30
25
20
15
10
5
0
0.1
Figure 10. RIN vs. Frequency
17dB
23dB
29dB
35dB
1
FREQUENCY (MHz)
10
Figure 11. Noise Figure vs. Frequency
AD8284
80
60
40
20
0
–60 –40 –20
0
20
CODE
40
Figure 12. Channel Offset Distribution (Gain = 17 dB)
60
80
60
40
20
0
–200
–100
0
CODE
100
200
Figure 13. Channel Offset Distribution (Gain = 35 dB)
Rev. D | Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD8284.PDF ] | |
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