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Datasheet LTC3721-1 PDF ( 特性, スペック, ピン接続図 )

部品番号 LTC3721-1
部品説明 Push-Pull PWM Controller
メーカ Linear
ロゴ Linear ロゴ 
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LTC3721-1 Datasheet, LTC3721-1 PDF,ピン配置, 機能
LTC3721-1
Push-Pull PWM Controller
FEATURES
High Efficiency Push-Pull PWM
1.5A Sink, 1A Source Output Drivers
Adjustable Push-Pull Dead-Time
Adjustable System Undervoltage Lockout and
Hysteresis
Adjustable Leading Edge Blanking
Low Start-Up and Quiescent Currents
Current Mode Operation
Single Resistor Slope Compensation
VCC UVLO and 25mA Shunt Regulator
Programmable Fixed Frequency Operation to 1MHz
Soft-Start, Cycle-by-Cycle Current Limiting and
Hiccup Mode Short-Circuit Protection
5V, 15mA Low Dropout Regulator
16-Pin SSOP and (4mm × 4mm) QFN Packages
U
APPLICATIO S
Telecommunications, Infrastructure Power Systems
Distributed Power Architectures
Server Power Supplies
High Density Power Modules
DESCRIPTIO
The LTC®3721-1 push-pull PWM controller provides all of
the control and protection functions necessary for com-
pact and highly efficient, isolated power converters. High
integration minimizes external component count, while
preserving design flexibility.
The robust push-pull output stages switch at half the
oscillator frequency. Dead-time is independently pro-
grammed with an external resistor. A UVLO program input
provides precise system turn-on and turn off voltages. The
LTC3721-1 features peak current mode control with pro-
grammable slope compensation and leading edge
blanking.
The LTC3721-1 features extremely low operating and
start-up currents and reliable short-circuit and
overtemperature protection. The LTC3721-1 is offered in
16-pin SSOP and (4mm × 4mm) QFN packages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
VIN
Isolated Push-Pull Converter
FROM
AUXILIARY
WINDING
VREF
UVLO
DRVA
DRVB
VCC CS
DPRG
LTC3721-1
CT
RLEB
VREF
SS COMP
FB GND
RCS
VOUT
VOUT
V+
COLL
COMP
LT1431
RTOP
RREF
RMID
GND-F GND-S
VOUT
+
37211 TA01
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LTC3721-1 pdf, ピン配列
LTC3721-1
ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 9.5V unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
Pulse Width Modulator
ROS Ramp Offset Voltage
Measured on COMP, CS = 0V
0.65 V
IRMP
ISLP
DCMAX
Ramp Discharge Current
Slope Compensation Current
Maximum Duty Cycle
CS = 1V, COMP = 0V, CT = 4V
Measured on CS, CT = 1V
CT = 2.25V
COMP = 4.5V
50
30
68
47 48.2 50
mA
µA
µA
%
DCMIN
Minimum Duty Cycle
COMP = 0V
0
%
DTADJ
Dead-Time
130 ns
Oscillator
OSCI Initial Accuracy
OSCT
VCC Variation
OSCV
CT Ramp Amplitude
Error Amplifier
TA = 25°C, CT = 270pF
VCC = 6.5V to 9.5V
Measured on CT
220 250 280
–3
3
2.35
kHz
%
V
VFB
FBI
AVOL
FB Input Voltage
FB Input Range
Open-Loop Gain
COMP = 2.5V, (Note 3)
Measured on FB, (Note 4)
COMP = 1V to 3V, (Note 3)
1.172
– 0.3
70
1.2
90
1.22
2.5
V
V
dB
IIB
VOH
VOL
ISOURCE
ISINK
Reference
Input Bias Current
Output High
Output Low
Output Source Current
Output Sink Current
COMP = 2.5V, (Note 3)
Load on COMP = –100µA
Load on COMP = 100µA
COMP = 2.5V
COMP = 2.5V
5 50
4.7 4.92
0.27 0.5
400 700
25
nA
V
V
µA
mA
VREF
REFLD
REFLN
REFTV
Initial Accuracy
Load Regulation
Line Regulation
Total Variation
TA = 25°C, Measured on VREF
Load on VREF = 100µA to 5mA
VCC = 6.5V to 9.5V
Line, Load and Temperature
4.925
4.900
5.00
2
1
5.000
5.075
15
10
5.100
V
mV
mV
V
REFSC
Short-Circuit Current
Push-Pull Outputs
VREF Shorted to GND
18 30 45
mA
DRVH(x) Output High Voltage
DRVL(x) Output Low Voltage
RDH(x) Pull-Up Resistance
RDL(x)
Pull-Down Resistance
TDR(x)
Rise-Time
TDF(x)
Fall-Time
Current Limit and Shutdown
IOUT(x) = –100mA
IOUT(x) = 100mA
IOUT(x) = –10mA to –100mA
IOUT(x) = –10mA to –100mA
COUT(x) = 1nF
COUT(x) = 1nF
9.2 V
0.17 V
2.9
1.7
10 ns
10 ns
CLPP
Pulse by Pulse Current Limit Threshold
Measured on CS
280 300 320
mV
CLSD
Shutdown Current Limit Threshold
Measured on CS
475 600 725
mV
CLDEL
Current Limit Delay to Output
100mV Overdrive on CS, (Note 2)
80 ns
SSI Soft-Start Current
SS = 2.5V
10 13 16
µA
sn37211 37211fs
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3Pages


LTC3721-1 電子部品, 半導体
LTC3721-1
PI DESCRIPTIO S (GN Package/UF Package)
VREF (Pin 1/Pin 15): Output of the 5.0V Reference. VREF is
capable of supplying up to 18mA to external circuitry. VREF
should be decoupled to GND with a 1µF ceramic capacitor.
DRVB (Pin 4/Pin 1): High Speed 1.5A Sink, 1A Source
Totem Pole MOSFET Driver. Connect to gate of external
push-pull MOSFET with as short a PCB trace as practical
to preserve drive signal integrity. A low value resistor
connected between DRVA and the MOSFET gate is op-
tional and will improve the gate drive signal quality if the
PCB trace from the driver to the MOSFET cannot be made
short.
VCC (Pin 5/Pin 2): Supply Voltage Input to the LTC3721-1
and 10.25V Shunt Regulator. The chip is enabled after VCC
has risen high enough to allow the VCC shunt regulator to
conduct current and the UVLO comparator threshold is
exceeded. Once the VCC shunt regulator has turned on,
VCC can drop to as low as 6V (typical) and maintain
operation. Bypass VCC to GND with a high quality 1µF or
larger ceramic capacitor to supply the transient currents
caused by the high speed switching and capacitive loads
presented by the on chip totem pole drivers.
DRVA (Pin 6/Pin 3): High Speed 1.5A Sink, 1A Source
Totem Pole MOSFET Driver. Connect to gate of external
push-pull MOSFET with as short a PCB trace as practical
to preserve drive signal integrity. A low value resistor
connected between DRVA and the MOSFET gate is op-
tional and will improve the gate drive signal quality if the
PCB trace from the driver to the MOSFET cannot be made
short.
GND (Pin 7/Pin 4, Pin 5, Pin 17): All circuits in the
LTC3721-1 are referenced to GND. Use of a ground plane
is highly recommended. VIN and VREF bypass capacitors
must be terminated with a star configuration as close to
GND as practical for best performance. For the 4mm ×
4mm QFN package only, the internal power (PGND) and
signal (SGND) buses are connected separately to pins 4
and 5 respectively, and the exposed pad must be soldered
to PCB ground.
CT (Pin 8/Pin 6): Timing Capacitor for the Oscillator. Use
a ±5% or better low ESR ceramic capacitor for best
results. CT ramp amplitude is 2.35V peak-to-peak
(typical).
DPRG (Pin 9/Pin 8): Programming Input for Push-Pull
Dead-Time. Connect a resistor between DPRG and VREF to
program the dead-time. The nominal voltage on DPRG is
2V.
CS (Pin 10/Pin 9): Input to Pulse-by-Pulse and Overload
Current Limit Comparators, Output of Slope Compensa-
tion Circuitry. The pulse-by-pulse comparator has a nomi-
nal 300mV threshold, while the overload comparator has
a nominal 600mV threshold. An internal switch discharges
CS to GND after every timing period. Slope compensation
current flows out of CS during the PWM period.
An external resistor connected from CS to the external
current sense resistor programs the amount of slope
compensation.
COMP (Pin 11/Pin 10): Error Amplifier Output, Inverting
Input to Phase Modulator.
RLEB (Pin 12/Pin 11): Timing Resistor for Leading Edge
Blanking. Use a 10k to 100k resistor connected between
RLEB and GND to program from 40ns to 310ns of leading
edge blanking of the current sense signal on CS for the
LTC3721-1. A ±1% tolerance resistor is recommended.
The nominal voltage on RLEB is 2V. If leading edge blank-
ing is not required, tie RLEB to VREF to disable.
6
sn37211 37211fs

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