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PDF LTC6754 Data sheet ( Hoja de datos )
| Número de pieza | LTC6754 | |
| Descripción | High Speed Rail-to-Rail Input Comparator | |
| Fabricantes | Linear | |
| Logotipo |  |
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Features
nn Low Propagation Delay: 1.8ns Typ.
nn Low Overdrive Dispersion: 1ns Typ.
(10mV to 125mV Overdrive)
nn High Toggle Rate: 890Mbps Typ.
nn LVDS Compatible Output Stage
nn Rail-to-Rail Inputs Extend Beyond Both Rails
nn Low Quiescent Current: 13.4mA
nn Supply Range: 2.4V to 5.25V
nn Features within the LTC6754 Family:
nn Separate Input and Output Supplies
nn Shutdown Pin for Reduced Power
nn Output Latch and Adjustable Hysteresis
nn SC70 and 3mm × 3mm QFN Packages
Applications
nn Clock and Data Recovery
nn Level Translation
nn High Speed Data Acquisition Systems
nn Window Comparators
nn High Speed Line Receivers
nn Time Domain Reflectometry
nn Time of Flight Measurements
nn Cable Drivers
Typical Application
High Speed Differential Line Receiver and LVDS Translator
with Excellent Common Mode Rejection
SMALL DIFFERENTIAL SIGNAL WITH
LARGE COMMON MODE COMPONENT
VCCI
+IN +
VCCO
Q
LTC6754
–IN –
VEE
Q
100Ω
6754 T01a
LTC6754
High Speed Rail-to-Rail
Input Comparator with
LVDS Compatible Outputs
Description
The LTC®6754 is a high speed rail-to-rail comparator with
LVDS compatible outputs. The LTC6754 exhibits 1.8ns of
propagation delay, only 1ns of dispersion (10mV to 125mV
overdrive) and a toggle rate up to 890Mbps.
The LTC6754 has rail-to-rail inputs, and will operate from
a 2.4V to 5.25V supply. For the QFN package, the LVDS
output is operated with a separate supply, providing isola-
tion between input and output circuitry, and allowing for
logic level translation.
In shutdown mode, power is reduced from 13.4mA to
under 1.1mA, and the comparator can wake up in 120ns.
The LTC6754 includes 4.5mV of hysteresis to minimize
instability. For the QFN package, a separate pin is available
to set the hysteresis from 0mV (off) up to 40mV. The QFN
version also features output latching to provide the ability
to quickly capture the state of the comparator.
The dispersion of only 1ns combined with excellent
propagation delay of 1.8ns makes the device an excel-
lent choice for timing critical applications. Similarly, the
890Mbps toggle rate and low jitter of 1.5psRMS (200mVP–P,
245.76MHz input) make the LTC6754 ideally suited for
high frequency line driver and clock recovery circuits.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Q–Q
100mV/DIV
0mV
Q–Q
+IN–IN
+IN, –IN
200mV/DIV
700mV
20ns/DIV
6754 F16
For more information www.linear.com/LTC6754
6754f
1
1 page  
LTC6754
Electrical Characteristics– oIvNe r=t hVeCMsp=e3ci0f0iemdVt,em+IpNe =ra –tuINre +r aVnOgVeER,DoRthIVeEr,w1i5s0emspVesctiefipca(sVtiizoCenC,sIRa=Lr=eV10Ca0tCΩTOA,==u22n5.le5°sCVs,)oLtEhT/eHhreYwSliTsde,eSnnHootDteeNds.pthinessfploeactiifnicga,tVioOnVEsRwDRhIiVcEh =a p5p0lmy V,
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
VCCI – VEE Input Supply Voltage (Note 5)
l 2.4
5.25 V
VCCO – VEE Output Supply Voltage (Note 5)
l 2.4
5.25 V
VCMR
Input Voltage Range (Note 7)
l VEE – 0.2
VCCI + 0.1
VOS Input Offset Voltage (Note 6)
–4.2
l –7.5
±0.7
4.2
7.5
mV
mV
TCVOS
Input Offset Voltage Drift
l 18
µV/ºC
VHYST
Input Hysteresis Voltage (Note 5)
LE/HYST pin floating
4.9 mV
CIN Input Capacitance
1.1 pF
RDM Differential Mode Resistance
55 kΩ
RCM Common Mode Resistance
6.5 MΩ
IB Input Bias Current
VCM = VEE + 0.3V
–3.8
l –4
–1.7
µA
μA
VCM = VCCI – 0.3V
0.5 1.3
µA
l 2.3 μA
IOS Input Offset Current
l –0.7
0.7 μA
CMRR_LVCM
CMRR_FR
PSRR
Common Mode Rejection Ratio,
Low VCM Region
Common Mode Rejection Ratio (Measured at
Extreme Ends of VCMR)
Power Supply Rejection Ratio
VCM = VEE – 0.2V to VCCI – 1.5V
VCM = VEE – 0.2V to VCCI+0.1V
V2.C4C5I V= tVoC5C.O25VVaried from
55
l 47
55
l 45.7
62
l 59.5
75
72
80
dB
dB
dB
dB
dB
dB
AVOL Open Loop Gain
Hysteresis Removed (Note 10)
53 dB
VOD Differential Output Voltage
l 260 345 420 mV
ΔVOD
Difference in VOD Between Complementary
Output States
l –15
±5
15
mV
VOCM
Output Common Mode Voltage
l 1.18 1.25 1.31
V
ΔVOCM
ODuiftfperuetnScteatinesVOCM Between Complementary
l –10
±1.8
10
mV
ISC_VEE
Short Circuit Current, through Either Output, both
Outputs Connected to VEE
ISC_OUT_SHORT Output Current, Complementary Outputs Shorted
l 15.5 mA
l 5 mA
IVCCI Input Stage Supply Current, Device On
Comparator On,
Input Section Supply Current
2.2 2.65 mA
l 2.9 mA
IVCCO
Output Stage Supply Current, Device On
Comparator On, Output Section Supply
Current
l
10.4 11.5
11.7
mA
mA
IVCC Total Supply Current, Device On
Comparator On, Single Supply Pin Version,
l
12.5 14.15
14.6
mA
mA
tR, tF Rise/Fall Time
20% to 80%
0.8 ns
tPD Propagation Delay (Note 8)
VOVERDRIVE = 50mV
2 2.9 ns
l 3.0 ns
tSKEW_RISEFALL Propagation Delay Skew, Rising to Falling Transition
50 ps
tSKEW_COMP Propagation Delay Skew, Q to Q
40 ps
tOD_DISP
Overdrive Dispersion
Overdrive Varied from 10mV to 125mV
1.1 ns
tCM_DISP
Common Mode Dispersion
VCM Varied from VEE – 0.2V to VCCI + 0.1V
200 ps
TR Toggle Rate
VIN = 200mVP–P Sine Wave, 50% Output Swing
800 Mbps
For more information www.linear.com/LTC6754
6754f
5
5 Page 
LTC6754
Applications Information
Circuit Description
The block diagram of the LTC6754 is shown in Figure 1.
There are differential inputs (+IN, –IN), a negative power
supply (VEE), two positive supply pins: VCCI for the input
stage and VCCO for the output stage, two output pins (Q and
Q), a pin for latching and adjusting hysteresis (LE/HYST),
and a pin to put the device in a low power mode (SHDN).
The signal path consists of a rail-to-rail input stage, an
intermediate gain stage and an output driver stage to an
output stage that sources or sinks 3.6mA between the two
output pins, depending on the polarity of the differential
input (+IN – –IN). The output stage also has a common
mode feedback network that keeps the average of Q and
Q approximately 1.26V. A Latching/Hysteresis interface
block allows the user to latch the output state and/or
remove or adjust the comparator input hysteresis. All of
the internal signal paths make use of low voltage swings
for high speed at low power.
Power Supply Configurations
The LTC6754UD (QFN Package) has separate positive
supply pins for the input and output stages that allow for
better isolation between the sensitive inputs and circuitry
connected to the output load by removing a direct path for
noise coupling through the positive supply. This feature
also allows the user the ability to decouple input signal
range from output stage power consumption (for example
by using a 5.25V input supply to allow for > 5V common
mode input range and a 2.4V output supply to minimize
total power consumption). Figure 2 shows a few possible
configurations.
For proper and reliable operation both supply pins should
be between 2.4V and 5.25V above the negative supply pin.
There are no restrictions regarding the sequence in which
the positive or negative supplies are applied as long as the
absolute maximum ratings are not violated.
Input Voltage Range and Offset
The LTC6754 family uses a rail-to-rail input stage that
consists of a PNP pair and an NPN pair that are active
over different input common mode ranges. The PNP pair
is active for inputs between VEE – 0.2V and approximately
VCCI – 1.5V (low common mode region of operation).
The NPN pair is active for inputs between approximately
VCCI – 1V and VCCI + 0.1V (high common mode region of
operation). Partial activation of both pairs occurs when
one input is in the low common mode region of operation
and the other input is in the high common mode region
of operation, or either of the inputs is between approxi-
mately VCCI – 1.5V and VCCI – 1V (transition region). The
device has small, trimmed offsets as long as both inputs
are completely in the low or high common mode region
of operation. In the transition region, the offset voltage
may increase. Applications that require good DC precision
should avoid the transition region.
Input Bias Current
When both inputs are in the low common mode region,
the input bias current is negative, with current flowing
out of the input pins. When both inputs are in the high
common mode region, the input bias current is positive,
with current flowing into the input pins. The input stage
has been designed to accommodate large differential input
voltages without large increases in input bias current. With
one input at the positive input supply rail and the other
input at the negative supply rail, the magnitude of the
input bias current at either pin is typically less than 3.5μA.
3V 3V
VCCI
+IN + VCCO Q
5V 2.4V
VCCI
+IN + VCCO Q
3.3V 5V
VCCI
+IN + VCCO Q
100Ω
–IN –
VEE
0V
Q
(a) SINGLE SUPPLY
100Ω
–IN –
VEE
0V
Q
(b) OUTPUT SUPPLY < INPUT SUPPLY
100Ω
–IN –
VEE
0V
Q
(c) OUTPUT SUPPLY > INPUT SUPPLY
6754 F02
Figure 2. Typical Power Supply Configurations Applicable to the LTC6754UD (QFN Package)
For more information www.linear.com/LTC6754
6754f
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet LTC6754.PDF ] | |
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