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uPD46185364B の電気的特性と機能

uPD46185364BのメーカーはRenesasです、この部品の機能は「18M-BIT QDR II SRAM 4-WORD BURST OPERATION」です。


製品の詳細 ( Datasheet PDF )

部品番号 uPD46185364B
部品説明 18M-BIT QDR II SRAM 4-WORD BURST OPERATION
メーカ Renesas
ロゴ Renesas ロゴ 




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uPD46185364B Datasheet, uPD46185364B PDF,ピン配置, 機能
μPD46185084B
μPD46185094B
μPD46185184B
μPD46185364B
Datasheet
18M-BIT QDRTM II SRAM
4-WORD BURST OPERATION
Description
R10DS0113EJ0200
Rev.2.00
Nov 09, 2012
The μPD46185084B is a 2,097,152-word by 8-bit, the μPD46185094B is a 2,097,152-word by 9-bit, the
μPD46185184B is a 1,048,576-word by 18-bit and the μPD46185364B is a 524,288-word by 36-bit synchronous
quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory
cell.
The μPD46185084B, μPD46185094B, μPD46185184B and μPD46185364B integrate unique synchronous
peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are
latched on the positive edge of K and K#. These products are suitable for application which require
synchronous operation, high speed, low voltage, high density and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
1.8 ± 0.1 V power supply
165-pin PLASTIC BGA (13 x 15)
HSTL interface
PLL circuitry for wide output data valid window and future frequency scaling
Separate independent read and write data ports with concurrent transactions
100% bus utilization DDR READ and WRITE operation
Four-tick burst for reduced address frequency
Two input clocks (K and K#) for precise DDR timing at clock rising edges only
Two output clocks (C and C#) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
Internally self-timed write control
Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed.
User programmable impedance output (35 to 70 Ω)
Fast clock cycle time : 3.3 ns (300 MHz), 4.0 ns (250 MHz)
Simple control logic for easy depth expansion
JTAG 1149.1 compatible test access port
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 1 of 38

1 Page





uPD46185364B pdf, ピン配列
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Pin Arrangement
123
A CQ# VSS/72M
A
B NC NC NC
C NC NC NC
D NC D4 NC
E NC NC Q4
F NC NC NC
G NC D5 Q5
H DLL# VREF VDDQ
J NC NC NC
K NC NC NC
L NC Q6 D6
M NC NC NC
N NC D7 NC
P NC NC Q7
R TDO TCK
A
165-pin PLASTIC BGA (13 x 15)
(Top View)
[μPD46185084B]
2M x 8
45678
W# NW1# K# NC/144M R#
A NC/288M K
NW0#
A
VSS A NC A VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VSS
VSS
VSS VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VSS
VSS
VSS VDDQ
VSS
VSS
VSS
VSS
VSS
VSS A A A VSS
AACAA
A A C# A A
9
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
10
VSS/36M
NC
NC
NC
D2
NC
NC
VREF
Q1
NC
NC
NC
NC
NC
TMS
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
A
D0 to D7
Q0 to Q7
R#
W#
NW0#, NW1#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Nibble Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
TMS
TDI
TCK
TDO
VREF
VDD
VDDQ
VSS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
Remarks 1. ×××# indicates active LOW.
2. Refer to Package Dimensions for the index mark.
3. 2A, 7A, 10A and 5B are expansion addresses : 10A for 36Mb
: 10A and 2A for 72Mb
: 10A, 2A and 7A for 144Mb.
: 10A, 2A, 7A and 5B for 288Mb.
2A and 10A of this product can also be used as NC.
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 3 of 38


3Pages


uPD46185364B 電子部品, 半導体
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Pin Arrangement
165-pin PLASTIC BGA (13 x 15)
(Top View)
[μPD46185364B]
512K x 36
1 2 3 4 5 6 7 8 9 10 11
A CQ# VSS/288M NC/72M W# BW2# K# BW1# R# NC/36M VSS/144M CQ
B Q27 Q18 D18
A BW3# K BW0# A
D17 Q17
Q8
C D27 Q28 D19 VSS
A
NC
A
VSS D16 Q7
D8
D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7
E Q29
D29
Q20 VDDQ
VSS
VSS
VSS VDDQ Q15
D6
Q6
F Q30
Q21
D21 VDDQ
VDD
VSS
VDD VDDQ D14
Q14
Q5
G D30
D22
Q22 VDDQ
VDD
VSS
VDD VDDQ Q13 D13
D5
H DLL#
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ VDDQ
VREF
ZQ
J D31
Q31
D23 VDDQ
VDD
VSS
VDD VDDQ D12
Q4
D4
K Q32
D32
Q23 VDDQ
VDD
VSS
VDD VDDQ Q12
D3
Q3
L Q33
Q24
D24 VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1
D2
N D34 D26 Q25 VSS
A
A
A VSS Q10 D9 D1
P Q35 D35 Q26
A
A
C
A
A Q9 D0 Q0
R TDO TCK
A
A
A C# A
A
A TMS TDI
A
D0 to D35
Q0 to Q35
R#
W#
BW0# to BW3#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
TMS
TDI
TCK
TDO
VREF
VDD
VDDQ
VSS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
Remarks 1. ×××# indicates active LOW.
2. Refer to Package Dimensions for the index mark.
3. 2A, 3A and 10A are expansion addresses : 9A for 36Mb
: 9A and 3A for 72Mb
: 9A, 3A and 10A for 144Mb
: 9A, 3A, 10A and 2A for 288Mb
2A and 10A of this product can also be used as NC.
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 6 of 38

6 Page



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部品番号部品説明メーカ
uPD46185364B

18M-BIT QDR II SRAM 4-WORD BURST OPERATION

Renesas
Renesas


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