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PDF 3850 Data sheet ( Hoja de datos )
| Número de pieza | 3850 | |
| Descripción | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER | |
| Fabricantes | Renesas | |
| Logotipo |  |
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✽This data sheet describes Spec. H and Spec. A of 3850 Group. The header of each page shows which specification is explained in
the page. The page explaining about both specifications shows the header of “Spec. H/A”.
3850 Group (Spec.H/A)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
REJ03B0036-0301Z
Rev.3.01
2003.06.20
3850 Group (Spec.H)
DESCRIPTION
The 3850 group (spec. H) is the 8-bit microcomputer based on the
740 family core technology.
The 3850 group (spec. H) is designed for the household products
and office automation equipment and includes serial I/O functions,
8-bit timer, and A-D converter.
FEATURES
qBasic machine-language instructions ...................................... 71
qMinimum instruction execution time .................................. 0.5 µs
(at 8 MHz oscillation frequency)
qMemory size
ROM ................................................................... 8K to 32K bytes
RAM ................................................................. 512 to 1024 bytes
qProgrammable input/output ports ............................................ 34
qInterrupts ................................................. 15 sources, 14 vectors
qTimers ............................................................................. 8-bit ✕ 4
qSerial I/O1 .................... 8-bit ✕ 1(UART or Clock-synchronized)
qSerial I/O2 ................................... 8-bit ✕ 1(Clock-synchronized)
qPWM ............................................................................... 8-bit ✕ 1
qA-D converter ............................................... 10-bit ✕ 5 channels
qWatchdog timer ............................................................ 16-bit ✕ 1
qClock generating circuit ..................................... Built-in 2 circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
qPower source voltage
In high-speed mode .................................................. 4.0 to 5.5 V
(at 8 MHz oscillation frequency)
In middle-speed mode ............................................... 2.7 to 5.5 V
(at 8 MHz oscillation frequency)
In low-speed mode .................................................... 2.7 to 5.5 V
(at 32 kHz oscillation frequency)
qPower dissipation
In high-speed mode .......................................................... 34 mW
(at 8 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode
Except M38507F8FP/SP ................................................... 60 µW
M38507F8FP/SP ............................................................. 450 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
qOperating temperature range .................................... –20 to 85°C
APPLICATION
Office automation equipment, FA equipment, Household products,
Consumer electronics, etc.
PIN CONFIGURATION (TOP VIEW)
VCC
VREF
AVSS
P44/INT3/PWM
P43/INT2/SCMP2
P42/INT1
P41/INT0
P40/CNTR1
P27/CNTR0/SRDY1
P26/SCLK1
P25/TxD
P24/RxD
P23
P22
VPP CNVSS
P21/XCIN
P20/XCOUT
RESET
XIN
XOUT
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42 P30/AN0
41 P31/AN1
40 P32/AN2
39 P33/AN3
38 P34/AN4
37 P00/SIN2
36 P01/SOUT2
35 P02/SCLK2
34 P03/SRDY2
33 P04
32 P05
31 P06
30 P07
29 P10/(LED0)
28 P11/(LED1)
27 P12/(LED2)
26 P13/(LED3)
25 P14/(LED4)
24 P15/(LED5)
23 P16/(LED6)
22 P17/(LED7)
: Flash memory version
Package type : FP ........................... 42P2R-A/E (42-pin plastic-molded SSOP)
Package type : SP ........................... 42P4B (42-pin plastic-molded SDIP)
Fig. 1 M38503MXH-XXXFP/SP pin configuration (spec. H)
Rev.3.01 2003.06.20 page 1 of 98
1
1 page  
3850 Group (Spec.H)
Table 1 Pin description (spec. H)
Pin
VCC, VSS
CNVSS
RESET
XIN
Name
Power source
CNVSS input
Reset input
Clock input
XOUT
Clock output
P00/SIN2
P01/SOUT2
P02/SCLK2
P03/SRDY2
P04–P07
P10–P17
P20/XCOUT
P21/XCIN
P22
P23
P24/RxD
P25/TxD
P26/SCLK1
P27/CNTR0/
SRDY1
I/O port P0
I/O port P1
I/O port P2
P30/AN0–
P34/AN4
P40/CNTR1
P41/INT0
P42/INT1
P43/INT2/SCMP2
I/O port P3
I/O port P4
P44/INT3/PWM
Functions
Function except a port function
•Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss.
•This pin controls the operation mode of the chip.
•Normally connected to VSS.
•Reset input pin for active “L”.
•Input and output pins for the clock generating circuit.
•Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
•When an external clock is used, connect the clock source to the XIN pin and leave the XOUT
pin open.
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually
programmed as either input or output.
• Serial I/O2 function pin
•CMOS compatible input level.
•CMOS 3-state output structure.
•P10 to P17 (8 bits) are enabled to output large current for LED drive.
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•CMOS compatible input level.
•P20, P21, P24 to P27: CMOS3-state output structure.
•P22, P23: N-channel open-drain structure.
• Sub-clock generating circuit I/O
pins (connect a resonator)
• Serial I/O1 function pin
•8-bit CMOS I/O port with the same function as port P0.
•CMOS compatible input level.
•CMOS 3-state output structure.
•8-bit CMOS I/O port with the same function as port P0.
•CMOS compatible input level.
•CMOS 3-state output structure.
• Serial I/O1 function pin/
Timer X function pin
• A-D converter input pin
• Timer Y function pin
• Interrupt input pins
• Interrupt input pin
• SCMP2 output pin
• Interrupt input pin
• PWM output pin
Rev.3.01 2003.06.20 page 5 of 98
5 Page 
3850 Group (Spec.H/A)
On-going Routine
Push return address
on stack
Interrupt request
(Note)
M (S) (PCH)
Execute JSR
(S) (S) – 1
M (S) (PCL)
(S) (S)– 1
Subroutine
POP return
address from stack
Execute RTS
(S) (S) + 1
(PCL) M (S)
(S) (S) + 1
(PCH) M (S)
M (S) (PCH)
(S) (S) – 1 Push return address
on stack
M (S) (PCL)
(S) (S) – 1
M (S) (PS)
Push contents of processor
status register on stack
(S) (S) – 1
Interrupt
Service Routine
Execute RTI
I Flag is set from “0” to “1”
Fetch the jump vector
(S) (S) + 1
(PS) M (S)
POP contents of
processor status
register from stack
(S) (S) + 1
(PCL) M (S)
(S) (S) + 1
POP return
address
from stack
(PCH) M (S)
Note: Condition for acceptance of an interrupt Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 8 Register push and pop at interrupt generation and subroutine call
Table 6 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Accumulator
Processor status register
PHA
PHP
Pop instruction from stack
PLA
PLP
Rev.3.01 2003.06.20 page 11 of 98
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 3850.PDF ] | |
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