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PDF HD74HC643 Data sheet ( Hoja de datos )
| Número de pieza | HD74HC643 | |
| Descripción | Octal Bus Transceivers | |
| Fabricantes | Renesas | |
| Logotipo |  |
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HD74HC640, HD74HC643
Octal Bus Transceivers (with 3-state outputs)
REJ03D0637-0200
(Previous ADE-205-517)
Rev.2.00
Mar 30, 2006
Description
Each device has an active enable G and a direction control input, DIR. When DIR is high, data flows from the A inputs
to the B outputs. When DIR is low, data flows from the B inputs to the A outputs. The HD74HC640 transfers inverted
data from one bus to other and the HD74HC643 transfers inverted data from the A bus to the B bus and true data from
the B bus to the A bus.
Features
• High Speed Operation: tpd = 12 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74HC640P
DILP-20 pin
PRDP0020AC-B
(DP-20NEV)
P
HD74HC640FPEL SOP-20 pin (JEITA)
PRSP0020DD-B
(FP-20DAV)
FP
HD74HC640RPEL
SOP-20 pin (JEDEC)
HD74HC643RPEL
PRSP0020DC-A RP
(FP-20DBV)
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
Function Table
Control Inputs
G DIR
LL
LH
HX
H : high level
L : low level
X : irrelevant
HD74HC640
B data to A bus
A data to B bus
Isolation
Operation
HD74HC643
B data to A bus
A data to B bus
Isolation
Rev.2.00 Mar 30, 2006 page 1 of 10
1 page  
HD74HC640, HD74HC643
Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Item
Propagation delay
time
Output enable
time
Output disable
time
Output rise/fall
time
Input capacitance
Symbol VCC (V)
tPHL 2.0
4.5
6.0
tPLH 2.0
4.5
6.0
tZL 2.0
4.5
6.0
tZH 2.0
4.5
6.0
tLZ 2.0
4.5
6.0
tHZ 2.0
4.5
6.0
tTLH 2.0
tTHL 4.5
6.0
Cin —
Ta = 25°C
Min Typ Max
— — 90
— 12 18
— — 15
— — 90
— 12 18
— — 15
— — 230
— 15 46
— — 39
— — 230
— 15 46
— — 39
— — 215
— 17 43
— — 37
— — 215
— 17 43
— — 37
— — 60
— 4 12
— — 10
— 5 10
Ta = –40 to +85°C
Min Max Unit
— 115 ns
— 23
— 20
— 115 ns
— 23
— 20
— 290 ns
— 58
— 49
— 290 ns
— 58
— 49
— 270 ns
— 54
— 46
— 270 ns
— 54
— 46
— 75 ns
— 15
— 13
— 10 pF
Test Circuit
HD74HC640
VCC
VCC
Test Conditions
Input
Pulse Generator
Zout = 50 Ω
Input
Pulse Generator
Zout = 50 Ω
G
DIR
S1
A1
B1
Output
1 kΩ S2
CL =
50 pF
OPEN
GND
VCC
TEST
tPLH / t PHL
tZH/ t HZ
tZL / t LZ
S2
OPEN
GND
VCC
Notes : 1. CL includes probe and jig capacitance.
2. A2–B2, A3–B3, A4–B4, A5–B5, A6–B6, A7–B7, A8–B8 are identical to above load circuit.
3. S1 is a input / output swich.
Rev.2.00 Mar 30, 2006 page 5 of 10
5 Page 
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
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© 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .6.0
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet HD74HC643.PDF ] | |
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