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HD74HC620 の電気的特性と機能

HD74HC620のメーカーはRenesasです、この部品の機能は「Octal Bus Transceivers」です。


製品の詳細 ( Datasheet PDF )

部品番号 HD74HC620
部品説明 Octal Bus Transceivers
メーカ Renesas
ロゴ Renesas ロゴ 




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HD74HC620 Datasheet, HD74HC620 PDF,ピン配置, 機能
HD74HC620, HD74HC623
Octal Bus Transceivers (with inverted 3-state outputs)
Octal Bus Transceivers (with 3-state outputs)
REJ03D0636-0200
(Previous ADE-205-516)
Rev.2.00
Mar 30, 2006
Description
This octal bus transceiver is designed for asynchronous two-way communication between data buses. The control
function implementation allows for maximum flexibility in timing.
This device allows data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the
logic levels at the enable inputs (GBA and GAB).
The enable inputs can be used to disable the device so that the buses are effectively isolated.
The dual-enable configuration gives these devices the capability to store data by simultaneous enabling of GBA and
GAB. Each output reinforces its input in this transceiver configuration. Thus, when both control inputs are enabled and
all other data sources to the two sets of bus lines are at high impedance, both sets of bus lines (16 in all) will remain at
their last states. The 8-bit codes appearing on the two sets of buses will be identical for the HD74HC623 or
complementary for the HD74HC620.
Features
High Speed Operation: tpd (Bus to Bus) = 12 ns typ (CL = 50 pF)
High Output Current: Fanout of 15 LSTTL Loads (QA to QH outputs)
Wide Operating Voltage: VCC = 2 to 6 V
Low Input Current: 1 µA max
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74HC620P
DILP-20 pin
PRDP0020AC-B
(DP-20NEV)
P
HD74HC620FPEL
HD74HC623FPEL
SOP-20 pin (JEITA)
PRSP0020DD-B
(FP-20DAV)
FP
HD74HC620RPEL
HD74HC623RPEL
SOP-20 pin (JEDEC)
PRSP0020DC-A
(FP-20DBV)
RP
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
Function Table
Enable Inputs
GBA
GAB
LL
HH
HL
LH
Operation
HD74HC620
HD74HC623
B data to A bus
B data to A bus
A data to B bus
A data to B bus
Isolation
Isolation
B data to A bus, A data to B bus B data to A bus, A data to B bus
Rev.2.00 Mar 30, 2006 page 1 of 11

1 Page





HD74HC620 pdf, ピン配列
HD74HC620, HD74HC623
Logic Diagram
HD74HC620
GBA
GAB
A1
VCC
A2
A3
A4
A5
A6
A7
A8
VCC
B1
B2
B3
B4
B5
B6
B7
B8
Rev.2.00 Mar 30, 2006 page 3 of 11


3Pages


HD74HC620 電子部品, 半導体
HD74HC620, HD74HC623
Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Item
Propagation delay
time
Output enable
time
Output disable
time
Output rise/fall
time
Input capacitance
Symbol VCC (V)
tPLH 2.0
tPHL 4.5
6.0
tZH 2.0
tZL 4.5
6.0
tHZ 2.0
tLZ 4.5
6.0
tTLH 2.0
tTHL 4.5
6.0
Cin —
Ta = 25°C
Min Typ Max
— — 100
— 12 20
— — 17
— — 150
— 12 30
— — 26
— — 150
— 16 30
— — 26
— — 60
— 4 12
— — 10
— 5 10
Ta = –40 to +85°C
Min Max
— 125
— 25
— 21
— 190
— 38
— 33
— 190
— 38
— 33
— 75
— 15
— 13
— 10
Unit
ns
ns
ns
ns
pF
Test Circuit
HD74HC620
VCC
VCC
Test Conditions
Input
Pulse Generator
Zout = 50
GBA
GAB
S1
A1
B1
Output
1 kS2
CL =
50 pF
OPEN
GND
VCC
TEST
tPLH / t PHL
tZH/ t HZ
tZL / t LZ
S2
OPEN
GND
VCC
Notes : 1. CL includes probe and jig capacitance.
2. A2–B2, A3–B3, A4–B4, A5–B5, A6–B6, A7–B7, A8–B8 are identical to above load circuit.
3. S1 is a input / output swich.
Rev.2.00 Mar 30, 2006 page 6 of 11

6 Page



ページ 合計 : 12 ページ
 
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共有リンク

Link :


部品番号部品説明メーカ
HD74HC620

Octal Bus Transceivers(with inverted 3-state outputs)

Hitachi Semiconductor
Hitachi Semiconductor
HD74HC620

Octal Bus Transceivers

Renesas
Renesas
HD74HC623

Octal Bus Transceivers(with inverted 3-state outputs)

Hitachi Semiconductor
Hitachi Semiconductor
HD74HC623

Octal Bus Transceivers

Renesas
Renesas


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