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PDF HD74HC563 Data sheet ( Hoja de datos )

Número de pieza HD74HC563
Descripción Octal Transparent Latches
Fabricantes Renesas 
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HD74HC563, HD74HC573
Octal Transparent Latches (with 3-state outputs)
REJ03D0629-0200
(Previous ADE-205-509)
Rev.2.00
Mar 30, 2006
Description
When the latch enable (LE) input is high, the Q outputs of HD74HC563 will follow the inversion of the D inputs and
the Q outputs of HD74HC573 will follow the D inputs. When the latch enable goes low, data at the D inputs will be
retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control
input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of
the storage elements.
Features
High Speed Operation: tpd (Data to Q, Q) = 11 ns typ (CL = 50 pF)
High Output Current: Fanout of 15 LSTTL Loads
Wide Operating Voltage: VCC = 2 to 6 V
Low Input Current: 1 µA max
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74HC563P
HD74HC573P
DILP-20 pin
PRDP0020AC-B
(DP-20NEV)
P
HD74HC563FPEL
SOP-20 pin (JEITA)
HD74HC573FPEL
PRSP0020DD-B
(FP-20DAV)
FP
HD74HC563RPEL
SOP-20 pin (JEDEC)
HD74HC573RPEL
PRSP0020DC-A
(FP-20DBV)
RP
HD74HC573TELL TSSOP-20 pin
PTSP0020JB-A
(TTP-20DAV)
T
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
ELL (2,000 pcs/reel)
Function Table
Inputs
Outputs
Output Control
Latch Enable
Data
HD74HC563
HD74HC573
L HH L H
LHLHL
L L X Q0 Q0
HXXZ Z
Q0 : level of Q before the indicated Steady-sate input conditions were established.
Q0 : complement of Q0 or level of Q before the indicated Steady-state input conditions were established.
Rev.2.00 Mar 30, 2006 page 1 of 10

1 page




HD74HC563 pdf
HD74HC563, HD74HC573
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Supply voltage range
Input / Output voltage
Input / Output diode current
Output current
VCC, GND current
Power dissipation
Storage temperature
VCC
VIN, VOUT
IIK, IOK
IO
ICC or IGND
PT
Tstg
–0.5 to 7.0
–0.5 to VCC +0.5
±20
±35
±75
500
–65 to +150
V
V
mA
mA
mA
mW
°C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
Recommended Operating Conditions
Item
Symbol
Ratings
Supply voltage
VCC 2 to 6
Input / Output voltage
Operating temperature
VIN, VOUT
Ta
0 to VCC
–40 to 85
Input rise / fall time*1
0 to 1000
tr, tf 0 to 500
0 to 400
Note: 1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
Unit
V
V
°C
ns
Conditions
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Electrical Characteristics
Item
Input voltage
Output voltage
Off-state output
current
Input current
Quiescent supply
current
Symbol
VIH
VIL
VOH
VOL
IOZ
Iin
ICC
VCC (V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
6.0
Ta = 25°C
Min Typ Max
1.5 — —
3.15 — —
4.2 — —
— — 0.5
— — 1.35
— — 1.8
1.9 2.0 —
4.4 4.5 —
5.9 6.0 —
4.18 — —
5.68 — —
— 0.0 0.1
— 0.0 0.1
— 0.0 0.1
— — 0.26
— — 0.26
— — ±0.5
— — ±0.1
— — 4.0
Ta = –40 to+85°C
Min Max Unit
Test Conditions
1.5 — V
3.15 —
4.2 —
— 0.5 V
— 1.35
— 1.8
1.9 — V Vin = VIH or VIL IOH = –20 µA
4.4 —
5.9 —
4.13 —
IOH = –6 mA
5.63 —
IOH = –7.8 mA
— 0.1 V Vin = VIH or VIL IOL = 20 µA
— 0.1
— 0.1
— 0.33
IOL = 6 mA
— 0.33
IOL = 7.8 mA
±5.0 µA Vin = VIH or VIL,
Vout = VCC or GND
±1.0 µA Vin = VCC or GND
— 40 µA Vin = VCC or GND, Iout = 0 µA
Rev.2.00 Mar 30, 2006 page 5 of 10

5 Page





HD74HC563 arduino
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
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http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
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© 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
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