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HD74HC165のメーカーはRenesasです、この部品の機能は「Parallel-load 8-bit Shift Register」です。 |
部品番号 | HD74HC165 |
| |
部品説明 | Parallel-load 8-bit Shift Register | ||
メーカ | Renesas | ||
ロゴ | |||
このページの下部にプレビューとHD74HC165ダウンロード(pdfファイル)リンクがあります。 Total 8 pages
HD74HC165
Parallel-load 8-bit Shift Register
REJ03D0581-0300
Rev.3.00
Jan 31, 2006
Description
This 8-bit serial shift register shifts data from QA to QH when clocked. Parallel inputs to each stage are enabled by a
low level at the Shift/Load input. Also included is a gated clock input and a complementary output from the eighth bit.
Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock inhibit function.
Holding either of the clock inputs high inhibits clocking, and holding either clock input low with the Shift/Load input
high enables the other clock input. Data transfer occurs on the positive going edge of the clock. Parallel loading is
inhibited as long as the Shift/Load input is high. When taken low, data at the parallel inputs is loaded directly into the
register independent of the state of the clock.
Features
• High Speed Operation: tpd (Clock to QH) = 21 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74HC165P
DILP-16 pin
PRDP0016AE-B
(DP-16FV)
P
HD74HC165FPEL SOP-16 pin (JEITA)
PRSP0016DH-B
(FP-16DAV)
FP
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
Function Table
Inputs
Parallel
Internal outputs
Shift/Load Clock Inhibit Clock
Serial
A ······ H
QA
QB
L
X
X
X a ······h
a
b
H
L
L
X
X
QA0
QB0
HL
HX
H QAn
HL
LX
L QAn
H
H
X
X
X
QA0
QB0
QAo to QHo = Outputs remain unchanged.
QAn to QGn = Data shifted from the previous stage on a positive edge at the clock input.
H : High level
L : Low level
X : Irrelevant
Output
QH
h
QH0
QGn
QGn
QH0
Rev.3.00, Jan 31, 2006 page 1 of 7
1 Page HD74HC165
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Supply voltage range
VCC
–0.5 to 7.0
V
Input / Output voltage
Input / Output diode current
Output current
VCC, GND current
Vin, Vout
IIK, IOK
IO
ICC or IGND
–0.5 to VCC +0.5
±20
±25
±50
V
mA
mA
mA
Power dissipation
Storage temperature
PT 500 mW
Tstg
–65 to +150
°C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
Recommended Operating Conditions
Item
Symbol
Ratings
Supply voltage
VCC 2 to 6
Input / Output voltage
VIN, VOUT
0 to VCC
Operating temperature
Ta –40 to 85
Input rise / fall time*1
0 to 1000
tr, tf 0 to 500
0 to 400
Note: 1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
Unit
V
V
°C
ns
Conditions
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Electrical Characteristics
Item
Input voltage
Output voltage
Input current
Quiescent supply
current
Symbol
VIH
VIL
VOH
VOL
Iin
ICC
VCC (V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
Ta = 25°C
Min Typ Max
1.5 — —
3.15 — —
4.2 — —
— — 0.5
— — 1.35
— — 1.8
1.9 2.0 —
4.4 4.5 —
5.9 6.0 —
4.18 — —
5.68 — —
— 0.0 0.1
— 0.0 0.1
— 0.0 0.1
— — 0.26
— — 0.26
— — ±0.1
— — 4.0
Ta = –40 to+85°C
Min Max Unit
Test Conditions
1.5 — V
3.15 —
4.2 —
— 0.5 V
— 1.35
— 1.8
1.9 — V Vin = VIH or VIL IOH = –20 µA
4.4 —
5.9 —
4.13 —
IOH = –4 mA
5.63
—
— IOH = –5.2 mA
0.1 V Vin = VIH or VIL IOL = 20 µA
— 0.1
— 0.1
— 0.33
IOL = 4 mA
— 0.33
IOL = 5.2 mA
— ±1.0 µA Vin = VCC or GND
— 40 µA Vin = VCC or GND, Iout = 0 µA
Rev.3.00, Jan 31, 2006 page 3 of 7
3Pages HD74HC165
Clock Inhibit
(Clock)
50%
VCC
(See notes 3)
Clock
(Clock Inhibit)
t rem
50% 50% 50%
GND
VCC
t su t w (clock)
F, H
(See notes
1 and 2)
50% 50%
50%
50%
t su t h
tw(load) t h
t w (load)
Shift / Load
QH
QH
90%
90%
50%
10%
6ns
t PHL
t PLH
50%
10%
6ns
t PHL
50%
90%
50%
10%
t THL
t PLH
90%
50%
10%
t TLH
t PHL
t PLH
90%
50%
10%
90%
50%
10%
50%
t TLH
t THL
50% 50%
t PLH
t PHL
t PHL
t PLH
50%
50%
t PLH
GND
VCC
GND
VCC
GND
VOH
t PHL
50%
VOL
VOH
VOL
Notes 1. The remaining six data inputs and the serial input are low.
2. Prior to test, high-level data is loaded into H input.
3. Disable while clock is high.
4. Input pulse : PRR ≤ 1MHz, duty cycle 50%
Rev.3.00, Jan 31, 2006 page 6 of 7
6 Page | |||
ページ | 合計 : 8 ページ | ||
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