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NE55410GR の電気的特性と機能

NE55410GRのメーカーはRenesasです、この部品の機能は「N-CHANNEL SILICON POWER LDMOS FET」です。


製品の詳細 ( Datasheet PDF )

部品番号 NE55410GR
部品説明 N-CHANNEL SILICON POWER LDMOS FET
メーカ Renesas
ロゴ Renesas ロゴ 




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NE55410GR Datasheet, NE55410GR PDF,ピン配置, 機能
DATA SHEET
LDMOS FIELD EFFECT TRANSISTOR
NE55410GR
N-CHANNEL SILICON POWER LDMOS FET
FOR 2 W + 10 W VHF to L-BAND SINGLE-END POWER AMPLIFIER
DESCRIPTION
The NE55410GR is an N-channel enhancement-mode LDMOS FET designed for driver 0.1 to 2.6 GHz PA, such
as, cellular base station amplifier, analog/digital TV-transmitters, and the other PA’s. This product has two different
FET's on one die manufactured using our NEWMOS technology (our WSi gate lateral MOS FET), and its nitride
surface passivation and quadruple layer aluminum silicon metalization offer a high degree of reliability.
<R>
FEATURES
• Two different FET’s (Q1 : Pout = 2 W, Q2 : Pout = 10 W) in one package
• Over 25 dB gain available by connecting two FET’s in series
: GL (Q1) = 13.5 dB TYP. (VDS = 28 V, IDset (Q1) = 20 mA, f = 2 140 MHz)
: GL (Q2) = 11.0 dB TYP. (VDS = 28 V, IDset (Q2) = 100 mA, f = 2 140 MHz)
• High 1 dB compression output power : PO (1 dB) (Q1) = 35.4 dBm TYP. (VDS = 28 V, IDset (Q1) = 20 mA, f = 2 140 MHz)
: PO (1 dB) (Q2) = 40.4 dBm TYP. (VDS = 28 V, IDset (Q2) = 100 mA, f = 2 140 MHz)
• High drain efficiency
: ηd (Q1) = 52% TYP. (VDS = 28 V, IDset (Q1) = 20 mA, f = 2 140 MHz)
: ηd (Q2) = 46% TYP. (VDS = 28 V, IDset (Q2) = 100 mA, f = 2 140 MHz)
• Low intermodulation distortion
: IM3 (Q1) = 40 dBc TYP. (VDS = 28 V, IDset (Q1+Q2) = 120 mA,
f = 2 132.5/2 147.5 MHz, Pout = 33 dBm (2 tones) )
• Single Supply (VDS : 3 V < VDS 32 V)
• Excellent Thermal Stability
• Surface mount type and Super low cost plastic package : 16-pin plastic HTSSOP
• Integrated ESD protection
• Excellent stability against HCI (Hot Carrier Injection)
APPLICATION
<R> • Digital cellular base station PA : W-CDMA/GSM/D-AMPS/N-CDMA/PCS etc.
• UHF-band TV transmitter PA
Caution Observe precautions when handling because these devices are sensitive to electrostatic discharge.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. PU10542EJ03V0DS (3rd edition)
Date Published January 2007 NS CP(N)
Printed in Japan
The mark <R> shows major revised points.
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
2004, 2007

1 Page





NE55410GR pdf, ピン配列
NE55410GR
THERMAL RESISTANCE (TA = +25°C)
Parameter
Channel to Case Resistance
Symbol
Rth (ch-c)
Test Conditions
MIN.
TYP.
2.5
MAX.
3.0
Unit
°C/W
RECOMMENDED OPERATING CONDITIONS (TA = +25°C)
<R>
<R>
<R>
<R>
Parameter
Drain to Source Voltage
Gate to Source Voltage
Input Power (Q1), CW
Input Power (Q2), CW
Average Output Power (Q1), CW Note
Average Output Power (Q2), CW Note
Symbol
VDS
VGS
Pin (Q1)
Pin (Q2)
PO (ave.) (Q1)
PO (ave.) (Q2)
MIN.
2.7
TYP.
28
3.3
15
20
MAX.
32
3.7
23
30
24
30
Note When mounting on the PWB that our company recommends.
Unit
V
V
dBm
dBm
dBm
dBm
ELECTRICAL CHARACTERISTICS (TA = +25°C)
Parameter
Q1
Gate to Source Leak Current
Drain to Source Leakage Current
Gate Threshold Voltage
Transconductance
Drain to Source Breakdown Voltage
Q2
Gate to Source Leak Current
Drain to Source Leakage Current
Gate Threshold Voltage
Transconductance
Drain to Source Breakdown Voltage
Symbol
Test Conditions
IGSS (Q1) VGSS = 5V
IDSS (Q1) VDSS = 65 V
Vth (Q1) VDS = 10 V, IDS = 1 mA
gm (Q1) VDS = 28 V, IDS = 20 mA
BVDSS (Q1) IDSS = 10 μA
IGSS (Q2) VGSS = 5V
IDSS (Q2) VDSS = 65 V
Vth (Q2) VDS = 10 V, IDS = 1 mA
gm (Q2) VDS = 28 V, IDS = 100 mA
BVDSS (Q2) IDSS = 10 μA
MIN. TYP. MAX. Unit
− − 1 μA
− − 1 mA
2.2 2.8 3.4
V
0.09
S
65 75
V
− − 1 μA
− − 1 mA
2.0 2.6 3.2
V
0.45
S
65 75
V
Data Sheet PU10542EJ03V0DS
3


3Pages


NE55410GR 電子部品, 半導体
NE55410GR
<R> S-PARAMETERS
S-parameters/Noise parameters are provided on our web site in a form (S2P) that enables direct import to a
microwave circuit simulator without keyboard input.
Click here to download S-parameters.
[RF and Microwave] [Device Parameters]
URL http://www.ncsd.necel.com/microwave/index.html
6 Data Sheet PU10542EJ03V0DS

6 Page



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部品番号部品説明メーカ
NE55410GR

N-CHANNEL SILICON POWER LDMOS FET

CEL
CEL
NE55410GR

N-CHANNEL SILICON POWER LDMOS FET

Renesas
Renesas


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