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PDF UPA2592T1H Data sheet ( Hoja de datos )
| Número de pieza | UPA2592T1H | |
| Descripción | N- AND P-CHANNEL MOSFET | |
| Fabricantes | Renesas | |
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DATA SHEET
MOS FIELD EFFECT TRANSISTOR
μ PA2592T1H
N- AND P-CHANNEL MOSFET
FOR SWITCHING
DESCRIPTION
The μ PA2592T1H is N- and P-channel MOSFETs designed for
DC/DC converters and power management applications of
portable equipments.
N- and P-channel MOSFETs are assembled in one package, to
contribute minimize the equipments.
PACKAGE DRAWING (Unit: mm)
2.9±0.1
0.65
8
5
A
0.17±0.05
0 to 0.025
FEATURES
• 2.5 V drive available
• Low on-state resistance
N-channel RDS(on)1 = 50 mΩ MAX. (VGS = 4.5 V, ID = 2 A)
RDS(on)2 = 65 mΩ MAX. (VGS = 2.5 V, ID = 2 A)
P-channel RDS(on)1 = 80 mΩ MAX. (VGS = −4.5 V, ID = −2 A)
RDS(on)2 = 140 mΩ MAX. (VGS = −2.5 V, ID = −1 A)
• Built-in gate protection diode
• Small and surface mount package (8-pin VSOF (2429))
1
0.32±0.05
S
4
0.05 M S A
N-channel 1: Source
2: Gate
7, 8: Drain
P-channel 3: Source
4: Gate
5, 6: Drain
ORDERING INFORMATION
PART NUMBER
μ PA2592T1H-T1-AT Note
μ PA2592T1H-T2-AT Note
LEAD PLATING
Pure Sn
PACKING
8 mm embossed taping
3000 p/reel
PACKAGE
8-pin VSOF (2429)
Note Pb-free (This product does not contain Pb in the external electrode and other parts.)
Marking: 2592
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest
version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for
availability and additional information.
Document No. G20215EJ1V0DS00 (1st edition)
Date Published February 2010 NS
Printed in Japan
2010
1 page  
μ PA2592T1H
TYPICAL CHARACTERISTICS (TA = 25°C)
(1) N-channel MOSFET
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
120
100
80
60
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
2
Mounted on FR-4 board of
25.4 mm x 25.4 mm x 0.8 mm
1.5
1 unit, 5 s
1
40
20
0
0 25 50 75 100 125 150 175
TA - Ambient Temperature - °C
FORWARD BIAS SAFE OPERATING AREA
100
10
RDS((VONG)SL=im41 .i5t eVd)
ID(DC)
1
ID(pulse)
PW
= 300 μs
11
0
0
110
m
1
11 m
m
1
s
s
1
s
5s
2 units, 5 s
0.5
0
0 25 50 75 100 125 150 175
TA - Ambient Temperature - °C
0.1
0.01
Single Pulse
Mounted on FR-4 board of
25.4 mm x 25.4 mm x 0.8 mm
PD(FET1):PD(FET2) = 1:1
0.1 1
10
VDS - Drain to Source Voltage - V
100
1000
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
PD (FET1) : PD (FET2) = 1 : 1
100
PD (FET1) : PD (FET2) = 1 : 0
10
1
1m
10 m
Single Pulse
Mounted on FR-4 board of 25.4 mm x 25.4 mm x 0.8 mm
100 m
1
10
PW - Pulse Width - s
100 1000
Data Sheet G20215EJ1V0DS
5
5 Page 
μ PA2592T1H
• The information in this document is current as of February, 2010. The information is subject to change without notice. For
actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date
specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an
NEC Electronics sales representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC
Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document.
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third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the
use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual
property rights of NEC Electronics or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in
semiconductor product operation and application examples. The incorporation of these circuits, software and information in
the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes
no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and
information.
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and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property
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above).
(M8E0909E)
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