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Datasheet DEI1188 PDF ( 特性, スペック, ピン接続図 )

部品番号 DEI1188
部品説明 8CH GND/OPEN DISCRETE INTERFACE IC W/ EXT HV PROTECTION
メーカ Device Engineering
ロゴ Device Engineering ロゴ 
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DEI1188 Datasheet, DEI1188 PDF,ピン配置, 機能
Device
Engineering
Incorporated
385 East Alamo Drive
Chandler, AZ 85225
Phone: (480) 303-0822
Fax: (480) 303-0824
E-mail: admin@deiaz.com
DEI1188
8CH GND/OPEN DISCRETE
INTERFACE IC W/ EXT HV
PROTECTION
FEATURES
Eight discrete inputs
o Senses GND/OPEN discrete signals.
o Meet input threshold and hysteresis requirements specified per AirBus ABD0100H specification.
ƒ Thresholds: 4.5V/10.5V, Hysteresis: 3V
o 1mA input current to prevent dry relay contacts.
o Internal isolation diode.
o Uses external series 3Kohm resistors on inputs to implement lightning transient immunity of 1600V and higher.
i.e.: DO160E, Section 22, Levels 4 and 5.
o Inputs protected from Lightning Induced Transients per DO160E, Section 22, Cat A3 and B3 plus waveform 5A
to 500V.
Serial I/O interface to read data register
o Direct interface to Serial Peripheral Interface (SPI) port.
o TTL/CMOS compatible inputs and Tristate output
o 10MHz Max Data Rate
o Serial input to expand Shift Register
Pin compatible with DEI1066
Logic Supply Voltage (VCC):
3.3V +/-5%
Analog Supply Voltage (VDD):
12.0V to 16.5V
16L SOIC EP package
PIN ASSIGNMENTS
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
1
DEI1188
16 VDD
GND
VCC
GND
SDI
/CS
SCLK
SDO
Figure 1 DEI1188 Pin Assignment (16 Lead SOIC)
©2009 Device Engineering Inc.
1 of 12
DS-MW-01188-01 Rev. D
07/21/2009

1 Page



DEI1188 pdf, ピン配列
SCLK
/CS
Control
Logic
ENB
SDO
DIN[1:8]
VDD VCC
DIN[1:8]
DISCRETE AFE
Channels 1 to 8
DOUT[1:8]
GND
SDI
SFT/LD
SDI
SCK
PDI[1:8]
DATA REG
8 bit Shift Register
w/ Parallel Input
SDO
(D0)
Figure 2 FUNCTION DIAGRAM
Vdd
always ON
100K
DINN
3K
(External)
7K
dp
17V
dn
11V
2K
dpw
200V
REFERENCE
SELECT
Vthreshold
Vdd Vcc
+
Comparator
DOUTN
-
Figure 3 DISCRETE AFE FUNCTION DIAGRAM
©2009 Device Engineering Inc.
3 of 12
DS-MW-01188-01 Rev. D
07/21/2009


3Pages


DEI1188 電子部品, 半導体
LIGHTNING PROTECTION
DINn inputs are designed to survive lightning induced transients as defined by RTCA DO160E, Section 22, Cat A3 and B3,
Waveforms 3, 4, and 5A, Level. They can withstand Level 3 stress and WF5A up to 500V (see figures below) with only the
external 3k Ohm series resistor for current limiting. Protection for higher stress levels can be achieved with the addition of
transient voltage suppressor (TVS) devices at the DINn pins. Select TVS clamp voltage < 450V. The 3Kseries resistor limits
the TVS surge current.
V/I
50%
0
25% to 75%
of Largest Peak
t
F = 1MHZ and 10MHZ
Figure 6 Voltage / Current Waveform 3
Waveform Source Impedance characteristics:
Waveform 3 Voc/Isc = 600V / 24A => 25 Ohms
Waveform 4 Voc/Isc = 300 V / 60 A => 5 Ohms
Waveform 5A Voc / Isc = 300V / 300A => 1 Ohm
Waveform 5A Voc / Isc = 500V / 500A => 1 Ohm
V
Peak
50%
T1 = 6.4uS
T2 = 70uS
0
T1
T2
t
Figure 7 Voltage Waveform 4
V/I
Peak
T1=40uS
T2=120uS
50%
0
T1
t
T2
Figure 8 Current/Voltage Waveform 5A
©2009 Device Engineering Inc.
6 of 12
DS-MW-01188-01 Rev. D
07/21/2009

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