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PDF SIO1007 Data sheet ( Hoja de datos )
| Número de pieza | SIO1007 | |
| Descripción | LPC Super I/O LPC IrDA Hot Docking Chip | |
| Fabricantes | Microchip | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SIO1007 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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SIO1007
LPC Super I/O LPC IrDA Hot Docking Chip with UART
Product Features
• 3.3 Volt Operation (5V tolerant)
• Programmable Wakeup Event Interface
(IO_PME# Pin)
• SMI Support (IO_SMI# Pin)
• GPIOs (16)
• Programmable internal pull-up resistors
• Two IRQ Input Pins
• XNOR Chain
• PC99a and ACPI 1.0 Compliant
• 64-Pin STQFP RoHS Compliant Package
• Intelligent Auto Power Management
• One Full Function Serial Port
- High Speed 16C550A Compatible UARTs
with Send/Receive 16-Byte FIFOs
- Supports 230k and 460k Baud
- Programmable Baud Rate Generator
- Modem Control Circuitry
• Infrared Communications Controller
- Three IR Ports
- Multi-Protocol Serial Communications Con-
trollers
- Two IrDA v1.2 (4Mbps), HPSIR, ASKIR, Con-
sumer IR Support
- One Consumer IR Port with support for NEC
PPM and RC5 with PME Wake-up Option
- Multiple Base I/O Address options, 15 IRQ
Options and 3 DMA Options
• LPC Bus Host Interface
- Supports LPC Bus frequencies of 19.2MHz to
33MHz
- Multiplexed Command, Address and Data
Bus
- 8-Bit I/O Transfers
- 8-Bit DMA Transfers
- 16-Bit Address Qualification
- Serial IRQ Interface Compatible with Serial-
ized IRQ Support for PCI Systems
- PCI nCLKRUN Support
- Power Management Event (IO_PME#) Inter-
face Pin
• LPC PortSwitch Interface
- Secondary Switchable LPC Interface (3.3V
only)
- Trusted cycles blocked
- Buffered 14 MHz output
- Switched PCI Clock output
Description
The Microchip SIO1007 is a 3.3V PC 99 and ACPI 1.0
compliant Super I/O Controller. The SIO1007 imple-
ments the LPC interface with the LPC PortSwitch
Interface. The LPC PortSwitch Interface is a hot-
switchable external Docking LPC interface with
trusted cycle block. The SIO1007 also features a full
16-bit internally decoded address bus, a Serial IRQ
interface with PCI nCLKRUN support, relocatable con-
figuration ports and three DMA channel options. The
part also includes 16 GPIO pins.
The SIO1007 incorporates one 8-pin 16C550A com-
patible UART. In addition, the SIO1007 provides a sec-
ond UART to support a Serial Infrared Interface that
complies with IrDA v1.2 (Fast IR), HPSIR, and ASKIR
formats, as well as Consumer IR. There is a second IR
port, which supports NEC PPM and RC5, as well as
Consumer IR protocols.
The SIO1007 incorporates sophisticated power control
circuitry (PCC). The PCC supports multiple low power
down modes. The SIO1007 also features Software
Configurable Logic (SCL) for ease of use. SCL allows
programmable system configuration of key functions
such as the UARTs.
The SIO1007 supports the ISA Plug-and-Play Standard
register set (Version 1.0a) and provides the recom-
mended functionality to support Windows ‘9x, 2K, ME,
XP and PC99. The I/O Address, DMA Channel and
Hardware IRQ of each device in the SIO1007 may be
reprogrammed through the internal configuration regis-
ters. There are 192 I/O address location options, a
Serialized IRQ interface, and three DMA channels.
2005 - 2015 Microchip Technology Inc.
DS00002020A-page 1
1 page  
2.0 PIN LAYOUT
FIGURE 2-1:
SIO1007 64 PIN STQFP
SIO1007
DLAD[1]
LAD[1]
DLAD[2]
LAD[2]
VCC
DLAD[3]
LAD[3]
VSS
DLPC_CLK_33
LPC_CLK_33
nDLDRQ1
nLDRQ1
nDLFRAME
nLFRAME
nDCLKRUN
nCLKRUN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64 PIN STQFP
48 VTR
47 nIO_PME
46 GP36
45 VSS
44 GP35
43 GP34
42 VCC
41 GP33
40 GP32
39 GP31
38 GP30
37 VSS
36 GP17
35 GP16/CIRTX
34 GP15/CIRRX
33 GP14 / IRQIN2
2005 - 2015 Microchip Technology Inc.
DS00002020A-page 5
5 Page 
SIO1007
Note 4-1
Note 4-2
Note 4-3
Note 4-4
Note 4-5
The LPCPD# pin may be tied high. The LPC interface will function properly if the PCI_RESET# signal
follows the protocol defined for the LRESET# signal in the "Low Pin Count Interface Specification".
The nRTS1/SYSOPT0 and the nDTS1/SYSOPT1 pins require external pullup/pull-down resistors to
set the default base I/O address for configuration to 0x002E, 0x004E, 0x162E, or 0x164E.
The LPC interface pins are 3.3 V only. These signals meet PCI DC specifications for 3.3V signaling.
These pins are not 5V tolerant and do not have ChiProtect.
These pins have an internal 45uA pull-up that is only active when the programmed via the GPIO Pull-
up Registers (CR37-CR38). The default state for the pin is for the pull-up to be enabled.
IIf CIRTX signal function is used and interfaced to a transceiver requiring duty cycle protection, an
external 5KOhm pulldown resistor should be used. In addition the an internal 45µA pullup resistor on
the CIRTX pin should be disabled by clearing the the GP16 bit in CR38 on page 82.
4.2 Buffer Type Description
Note: The buffer type values are specified at VCC=3.3V.
TABLE 4-2: BUFFER TYPES
Buffer Type
Description
I
IS
O6
O8
OD8
IO8
IS/O8
O12
OD12
IO12
OP14
O24
PCI_IO
PCI_O
PCI_I
PCI_ICLK
Input, TTL Compatible.
Input with Schmitt Trigger.
Output, 6mA sink, 3mA source.
Output, 8mA sink, 4mA source.
Open Drain Output, 8mA sink.
Input/Output, 8mA sink, 4mA source.
Input with Schmitt Trigger/Output, 8mA sink, 4mA source.
Output, 12mA sink, 6mA source.
Open Drain Output, 12mA sink.
Input/Output, 12mA sink, 6mA source.
Output, 14mA sink, 14mA source.
Output, 24mA sink, 12mA source.
Input/Output. These pins must meet the PCI 3.3V AC and DC Characteristics.
(Note 4-6)
Output. These pins must meet the PCI 3.3V AC and DC Characteristics. (Note 4-6)
Input. These pins must meet the PCI 3.3V AC and DC Characteristics. (Note 4-6)
Clock Input. These pins must meet the PCI 3.3V AC and DC Characteristics and
timing. (Note 4-7)
Note 4-6
Note 4-7
See the “PCI Local Bus Specification,” Revision 2.1, Section 4.2.2.
See the “PCI Local Bus Specification,” Revision 2.1, Section 4.2.2 and 4.2.3.
2005 - 2015 Microchip Technology Inc.
DS00002020A-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SIO1007.PDF ] | |
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