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PDF SPEAR320S Data sheet ( Hoja de datos )
| Número de pieza | SPEAR320S | |
| Descripción | Embedded MPU | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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SPEAr320S
Embedded MPU with ARM926 core
for industrial and consumer applications
Datasheet − production data
Features
■ ARM926EJ-S CPU core, up to 333 MHz
■ Multilayer bus matrix, up to 166 MHz
■ Internal memories: 32 KB ROM, 8 KB SRAM
■ Memory interfaces:
– DDR controller (DDR2-666, LPDDR-333),
8-/16-bit
– Serial NOR Flash controller
– Parallel NAND Flash controller, 8-/16-bit
data bus
– Parallel NOR Flash/FPGA interface,
8-/16-bit data bus
■ Connectivity:
– 2 x USB 2.0 Host ports (integrated PHY)
– 1 x USB 2.0 Device port (integrated PHY)
– 2 x Fast Ethernet ports (external MII/RMII
PHY)
– 1 x MMC-SD card/SDIO controller
– 2 x CAN 2.0 ports
– 7 x UART ports
– 3 x I2C ports: master/slave
– 3 x synchronous serial ports,
SPI/Microwire/TI protocols, master/slave
– 1 x RS485 interface
– 1 x fast IrDA interface
– 1 x legacy parallel port (IEEE 1284), slave
mode
– 10-bit ADC, 8 channels, 1 Msps
– Up to 102 GPIOs with interrupt capability
■ HMI support:
– LCD display controller, up to XGA
(1024 x 768, 24 bpp)
– Resistive touchscreen interface
– JPEG codec accelerator
– 1 x I2S digital audio port
■ Security
– Cryptographic co-processor
LFBGA289 (15 x 15 x 1.7 mm)
■ Miscellaneous functions:
– System controller, vectored interrupt
controller, watchdog, real-time clock
– Dynamic power-saving features
– 8-channel DMA controller
– 6 x 16-bit general purpose timers with
prescaler and 4 capture inputs
– 4 x PWM generators
– Debug and trace interfaces: JTAG/ETM
Applications
The SPEAr320S embedded MPU is configurable
for a range of industrial and consumer
applications such as:
■ Human machine interface (HMI) terminals
■ Factory automation / PLCs
■ Medical equipment
■ Smart energy meters and gateways
■ VoIP phones
■ Small printers
The device is hardware-compliant to the support
of both real-time (RTOS) and high-level (HLOS)
operating systems, such as Linux and Windows
Embedded Compact 7.
Table 1. Device summary
Order code
Temp
range, °C
Package Packing
LFBGA289
SPEAR320S-2 -40 to 85 (15x15 mm,
pitch 0.8 mm)
Tray
September 2012
This is information on a product in full production.
Doc ID 022508 Rev 2
1/113
www.st.com
1
1 page  
SPEAr320S
Contents
5.18 UART timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Appendix A Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Doc ID 022508 Rev 2
5/113
5 Page 
SPEAr320S
2 Device functions
Device functions
2.1 CPU subsystem
The core of the SPEAr320S is an ARM926EJ-S reduced instruction set computer (RISC)
processor.
Main features:
● Supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling the user to trade
off between high performance and high code density. It also includes features for
efficient execution of Java byte codes.
● The ARM CPU can be clocked at a frequency up to 333 MHz and includes both an
instruction (16 KB) and a data cache (16 KB). In addition to the capability of running
any real-time operating system (RTOS) available for ARM9 processors, the
ARM926EJ-S subsystem also provides a memory management unit (MMU) that
enables to support high-level operating systems (HLOS) like Linux and Windows
Embedded Compact 7.
● Includes an embedded trace module (ETM Medium+) for real-time CPU activity tracing
and debugging. It supports 4-bit and 8-bit normal trace mode and 4-bit demultiplexed
trace mode, with normal or half-rate clock.
For detailed information, please refer to the following public documents available from the
ARM Ltd. website:
● CPU Core:
ARM9EJ-S, Technical Reference Manual, Revision: r1p2
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0222b/DDI0222.pdf
● CPU Subsystem:
ARM926EJ-S, Technical Reference Manual, Revision: r0p5
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0198e/DDI0198E_arm926ejs_r0p
5_trm.pdf
2.2 Internal memories (BootROM/SRAM)
SPEAr320S integrates two embedded memories:
● 32 KB ROM (BootROM), storing a factory-defined device bootstrap firmware.
● 8 KB Static RAM (SRAM), partly used by bootstrap firmware, but also available as
general-purpose memory after system startup.
The firmware in BootROM is automatically executed after SPEAr320S reset and supports
the following bootstrap modes:
● Boot from serial NOR Flash
● Boot from parallel NAND Flash
● Boot from parallel NOR Flash
● Boot from USB Device port
● Boot from UART0
● Boot from Ethernet (MII0)
Doc ID 022508 Rev 2
11/113
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SPEAR320S.PDF ] | |
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