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PDF IRS26302DJPBF Data sheet ( Hoja de datos )
| Número de pieza | IRS26302DJPBF | |
| Descripción | FULLY PROTECTED 3-PHASE BRIDGE PLUS ONE GATE DRIVER | |
| Fabricantes | International Rectifier | |
| Logotipo |  |
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Data Sheet No. PD 60321A
IRS26302DJPBF
FULLY PROTECTED 3-PHASE BRIDGE PLUS ONE GATE
DRIVER
Features
Product Summary
• Floating channel designed for bootstrap operation, fully
• operational to +600 V
Topology
3 Phase
• Tolerant to negative transient voltage – dV/dt immune
• Full three phase gate driver plus one low side driver
• Undervoltage lockout for all channels
VOFFSET
VOUT
≤ 600 V
10 V – 20 V
• Cross-conduction prevention logic
• Power-on reset
Io+ & I o- (typical)
200 mA & 350 mA
• Integrated bootstrap diode for floating channel supply
Deadtime (typical)
• Over current protection on: DC-(Itrip), DC+(Ground fault),
290 ns
PFCtrip/BRtrip (PFC/Brake protection).
• Single pin fault diagnostic function
Package
• Diagnostic protocol to address fault register
• Self biasing for ground fault detection high voltage circuit
• 3.3 V logic compatible
• Lower di/dt gate drive for better noise immunity
• Externally programmable delay for automatic fault clear
• RoHS compliant
Typical Applications
• Air conditioners inverters
44-Lead PLCC
• Micro/Mini inverter drives
• General purpose inverter
• Motor control
Typical Connection Diagram
www.irf.com
3-Jul-09
© 2009 International Rectifier
1 page  
IRS26302DJ
Qualification Information†
Qualification Level
Moisture Sensitivity Level
ESD
IC Latch-Up Test
RoHS Compliant
Machine Model
Human Body Model
Charged Device Model
Industrial††
(per JEDEC JESD 47E)
Comments: This family of ICs has passed JEDEC’s
Industrial qualification. IR’s Consumer qualification level is
granted by extension of the higher Industrial level.
PLCC44
MSL3†††
(per IPC/JEDEC J-STD-020C)
Class B
(per JEDEC standard JESD22-A114D)
Class 2
(per EIA/JEDEC standard EIA/JESD22-A115-A)
Class IV
(per JEDEC standard JESD22-C101C)
Class I, Level A
(per JESD78A)
Yes
† Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
†† Higher qualification ratings may be available should the user have such requirements. Please contact your
International Rectifier sales representative for further information.
††† Higher MSL ratings may be available for the specific package types listed here. Please contact your
International Rectifier sales representative for further information.
www.irf.com
© 2009 International Rectifier
5
5 Page 
IRS26302DJ
Dynamic Electrical Characteristics
VCC= VB = 15 V, VS = VSS = COM, TA = 25 oC, and CL = 1000 pF unless otherwise specified.
Symbol Definition
Min Typ Max Units
Test Conditions
tITRIPPFC/tITRI
PBR
ITRIP to PFCout/BRout shutdown
propagation delay
400
620
850
VITRIP = -1 V ≥ 2 V to
PFCOUT/BROUT = 15 V ≥ 0 V
tPFCTRIPFLT
/tBRTRIPFLT
PFCTRIP/BRTRIP to fault time
700 1000 1500
VPFCTRIP/VBRTRIP = 1V ≥
-1.5 V V to FLT/En = 3.3 V ≥
0V
tPFCTRIPOUT
/tBRTRIPOUT
PFCTRIP/BRTRIP to output
shutdown propagation delay
400 600 950
VPFCTRIP/VBRTRIP = 1V ≥
-1.5 V to LOx/Hox = 15 V ≥ 0
V
tPFCTRIPPFC
/tBRTRIPPFC
PFCTRIP/BRTRIP to PFC output
shutdown propagation delay
320 500 850
VPFCTRIP/VBRTRIP = 1V ≥
-1.5 V to PFCOUT = 15 V ≥ 0 V
tPFCTRIPBLK
/tBRTRIPBLK
PFCTRIP/BRTRIP blanking time
150 450 750
tGFTRIPFLT
GFTRIP to fault time
1000 1400 1800
VGF = VDC ≥ VDC -1 V to
FLT/En = 15 V ≥ 0 V
tGFTRIPOUT
GFTRIP to output shutdown
propagation delay
700 1000 1300
VGF = VDC ≥ VDC -1 V to
LOx/Hox = 15 V ≥ 0 V
tGFTRIPPFC
GFTRIP to PFC output shutdown
propagation delay
600 900 1200 ns
VGF = VDC ≥ VDC -1 V to
PFCOUT = 15 V ≥ 0 V
tGFTRIPBLK
GFTRIP blanking time
150 300 550
tENOUT
EN on to output propagation delay
300
400
500
VEN = 0 V ≥ 3.3 V, LINx/HINx
= 3.3 V to LOx/Hox = 0 V ≥ 15
V
tSDOUT
EN off to output shutdown
propagation delay
320 440 560
VEN = 3.3 V ≥ 0 V, LINx/HINx
= 3.3 V to LOx/Hox = 15 V ≥ 0
V
tENPFC/tENB
R
EN on to PFC/Brake output
propagation delay
200 320 500
VEN = 0 V ≥ 3.3 V ,
PFCIN/BRIN = 3.3 V to
PFCOUT/BROUT = 0 V ≥ 15 V
tSDPFC/tSDB
R
EN off to output shutdown PFC/Brake
propagation delay
200
360
500
VEN = 3.3 V ≥ 0 V,
PFCIN/BRIN = 3.3 V to
PFCOUT/BROUT =15 V ≥ 0 V
tHANDSHAKE
tDIAGIN
Input to Hand shake mode delay
Input to DIAG mode in delay
300 500 700
See fault diagnostic state
diagram
tDIAGOUT
Input to DIAG mode out delay
Note 1: A shoot-through prevention logic prevents LO1,2,3 and HO1,2,3 for each channel from turning on simultaneously.
Note 2: UVCC is not latched, when VCC > UVCC, FAULT return to high impedance.
Note 3: When ITRIP <VITRIP, FAULT returns to high-impedance after RCIN pin becomes greater than 8 V (@ VCC = 15 V)
www.irf.com
© 2009 International Rectifier
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IRS26302DJPBF.PDF ] | |
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