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8T49N286 の電気的特性と機能

8T49N286のメーカーはIntegrated Device Technologyです、この部品の機能は「NG Octal Universal Frequency Translator」です。


製品の詳細 ( Datasheet PDF )

部品番号 8T49N286
部品説明 NG Octal Universal Frequency Translator
メーカ Integrated Device Technology
ロゴ Integrated Device Technology ロゴ 




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8T49N286 Datasheet, 8T49N286 PDF,ピン配置, 機能
FemtoClock® NG Octal Universal
Frequency Translator
8T49N286
Datasheet
General Description
The 8T49N286 has two independent, fractional-feedback PLLs that
can be used as jitter attenuators and frequency translators. It is
equipped with six integer and two fractional output dividers, allowing
the generation of up to eight different output frequencies, ranging
from 8kHz to 1GHz. Four of these frequencies are completely
independent of each other and the inputs. The other four are related
frequencies. The eight outputs may select among LVPECL, LVDS,
HCSL or LVCMOS output levels.
This functionality makes it ideal to be used in any frequency
translation application, including 1G, 10G, 40G and 100G
Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T
G.709 (2009) FEC rates. The device may also behave as a frequency
synthesizer.
The 8T49N286 accepts up to four differential or single-ended input
clocks and a crystal input. Each of the two internal PLLs can lock to
different input clocks which may be of independent frequencies. The
other two input clocks are intended for redundant backup of the
primary clocks and must be related in frequency to their primary.
The device supports hitless reference switching between input
clocks. The device monitors all input clocks for Loss of Signal (LOS),
and generates an alarm when an input clock failure is detected.
Automatic and manual hitless reference switching options are
supported. LOS behavior can be set to support gapped or un-gapped
clocks.
The 8T49N286 supports holdover for each PLL. The holdover has an
initial accuracy of ±50ppB from the point where the loss of all
applicable input reference(s) has been detected. It maintains a
historical average operating point for each PLL that may be returned
to in holdover at a limited phase slope.
The device places no constraints on input to output frequency
conversion, supporting all FEC rates, including the new revision of
ITU-T Recommendation G.709 (2009), most with 0ppm conversion
error.
Each PLL has a register-selectable loop bandwidth from 1.4Hz to
360Hz.
Each output supports individual phase delay settings to allow
output-output alignment.
The device supports Output Enable inputs and Lock, Holdover and
LOS status outputs.
The device is programmable through an I2C interface. It also supports
I2C master capability to allow the register configuration to be read
from an external EEPROM. The user may select whether the
programming interface uses I2C protocols or SPI protocols, however
in SPI mode, read from the external EEPROM is not supported.
Applications
OTN or SONET / SDH equipment Line cards (up to OC-192, and
supporting FEC ratios)
OTN de-mapping (Gapped Clock and DCO mode)
Gigabit and Terabit IP switches / routers including support of
Synchronous Ethernet
SyncE (G.8262) applications
Wireless base station baseband
Data communications
100G Ethernet
Features
Supports SDH/SONET and Synchronous Ethernet clocks
including all FEC rate conversions
<0.3ps RMS Typical Jitter (including spurs), 12kHz to 20MHz
Operating modes: locked to input signal, holdover and free-run
Initial holdover accuracy of ±50ppb
Accepts up to four LVPECL, LVDS, LVHSTL, HCSL or LVCMOS
input clocks
Accepts frequencies ranging from 8kHz up to 875MHz
Auto and manual input clock selection with hitless switching
Clock input monitoring, including support for gapped clocks
Phase-Slope Limiting and Fully Hitless Switching options to
control output phase transients
Operates from a 10MHz to 40MHz fundamental-mode crystal
Generates 8 LVPECL / LVDS / HCSL or 16 LVCMOS output
clocks
Output frequencies ranging from 8kHz up to 1.0GHz (diff)
Output frequencies ranging from 8kHz to 250MHz (LVCMOS)
Eight General Purpose I/O pins with optional support for status
and control
Eight Output Enable control inputs
Lock, Holdover and Loss-of-Signal status outputs
Open-drain Interrupt pin
Write-protect pin to prevent configuration registers being altered
Nine programmable loop bandwidth settings for each PLL from
1.4Hz to 360Hz.
Optional Fast Lock function
Programmable output phase delays in steps as small as 16ps
Register programmable through I2C / SPI or via external I2C
EEPROM
Bypass clock paths for system tests
Power supply modes:
VCC / VCCA / VCCO
3.3V / 3.3V / 3.3V
3.3V / 3.3V / 2.5V
3.3V / 3.3V / 1.8V (LVCMOS)
2.5V / 2.5V / 3.3V
2.5V / 2.5V / 2.5V
2.5V / 2.5V / 1.8V (LVCMOS)
-40°C to 85°C ambient operating temperature
Package: 72QFN, lead-free RoHs (6)
©2016 Integrated Device Technology, Inc.
1
Revision 7, October 27, 2016

1 Page





8T49N286 pdf, ピン配列
Pin Assignment
VEE
nQ1
Q1
VCCO1
nWP
nRST
VEE
nQ0
Q0
VCCO0
nINT
VCCA
CAP0_REF
CAP0
PLL_BYP
VCCA
VCCA
VCCA
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
55 36
56 35
57 34
58 33
59 32
60 8XXXXXX
61
31
30
62 29
63 8T49N286 28
64 27
65 26
66 25
67 24
68 23
69 22
70 21
71 20
72 19
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
VEE
nQ2
Q2
VCCO2
nI2C_SPI
GPIO[0]
VEE
nQ3
Q3
VCCO3
GPIO[1]
VCCA
CAP1_REF
CAP1
VCC
VCCA
VCCA
VCCA
72-pin, 10mm x 10mm VFQFN Package
Figure 2. Pinout Drawing
8T49N286 Datasheet
©2016 Integrated Device Technology, Inc.
3
Revision 7, October 27, 2016


3Pages


8T49N286 電子部品, 半導体
8T49N286 Datasheet
Table 2. Pin Characteristics, VCC = VCCOX = 3.3V±5% or 2.5V±5%
Symbol
Parameter
Test Conditions
CIN
RPULLUP
Input Capacitance; NOTE 1
Internal Pullup
Resistor
nRST, nWP,
SDATA / SDO,
SCLK / SCLK
nINT
GPIO[7:0]
RPULLDOWN
Internal Pulldown Resistor
LVCMOS
Q[0:1], Q[4:7]
VCCOX = 3.465V
LVCMOS Q[2:3]
LVCMOS
Q[0:1], Q[4:7]
VCCOX = 3.465V
VCCOX = 2.625V
Power
LVCMOS Q[2:3]
CPD
Dissipation
Capacitance
LVCMOS
Q[0:1], Q[4:7]
(per output pair) LVCMOS Q[2:3]
VCCOX = 2.625V
VCCOX = 1.89V
VCCOX = 1.89V
LVDS, HCSL or
LVPECL Q[0:1],
Q[4:7]
VCCOx = 3.465V or 2.625V
LVDS, HCSL or
LVPECL Q[2:3]
VCCOx = 3.465V or 2.625V
ROUT
Output
Impedance
GPIO[7:0]
LVCMOS
Q[7:0], nQ[7:0]
Output HIGH
Output LOW
NOTE: VCCOX denotes: VCCO0 through VCCO7.
NOTE 1: This specification does not apply to OSCI and OSCO pins.
Minimum
Typical
3.5
Maximum Units
pF
51 k
50 k
5.1 k
51 k
14.5 pF
18.5 pF
13 pF
17.5 pF
12.5 pF
17 pF
2 pF
4.5 pF
5.1 k
25
20
©2016 Integrated Device Technology, Inc.
6
Revision 7, October 27, 2016

6 Page



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共有リンク

Link :


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