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PDF 8T49N285 Data sheet ( 特性 )

部品番号 8T49N285
部品説明 NG Octal Universal Frequency Translator
メーカ Integrated Device Technology
ロゴ Integrated Device Technology ロゴ 

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8T49N285 Datasheet, 8T49N285 PDF,ピン配置, 機能
FemtoClock® NG Octal Universal
Frequency Translator
8T49N285
Datasheet
General Description
The 8T49N285 has a fractional-feedback PLL that can be used as a
jitter attenuator or frequency translator. It is equipped with six integer
and two fractional output dividers, allowing the generation of up to 8
different output frequencies, ranging from 8kHz to 1GHz. Three of
these frequencies are completely independent of each other and the
inputs. The other five are related frequencies. The eight outputs may
select among LVPECL, LVDS, HCSL or LVCMOS output levels.
This functionality makes it ideal to be used in any frequency
translation application, including 1G, 10G, 40G and 100G
Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T
G.709 (2009) FEC rates. The device may also behave as a frequency
synthesizer.
The 8T49N285 accepts up to two differential or single-ended input
clocks and a crystal input. The PLL can lock to either input clock, but
both input clocks must be related in frequency.
The device supports hitless reference switching between input
clocks. The device monitors both input clocks for Loss of Signal
(LOS). It generates an alarm when an input clock failure is detected.
Automatic and manual hitless reference switching options are
supported. LOS behavior can be set to support gapped or un-gapped
clocks.
The 8T49N285 supports holdover with an initial accuracy of ±50ppB
from the point where the loss of all applicable input reference(s) has
been detected. It maintains a historical average operating point that
may be returned to in holdover at a limited phase slope.
The device places no constraints on input to output frequency
conversion, supporting all FEC rates, including the new revision of
ITU-T Recommendation G.709 (2009), most with 0ppm conversion
error.
The PLL has a register-selectable loop bandwidth from 1.4Hz to
360Hz.
Each output supports individual phase delay settings to allow
output-output alignment.
The device supports Output Enable inputs and Lock, Holdover and
LOS status outputs.
The device is programmable through an I2C interface. It also
supports I2C master capability to allow the register configuration to
be read from an external EEPROM.
Applications
• OTN or SONET / SDH equipment Line cards (up to OC-192, and
supporting FEC ratios)
• OTN de-mapping (Gapped Clock and DCO mode)
• Gigabit and Terabit IP switches / routers including support of
Synchronous Ethernet
• SyncE (G.8262) applications
• Wireless base station baseband
• Data communications
• 100G Ethernet
Features
Supports SDH/SONET and Synchronous Ethernet clocks
including all FEC rate conversions
<0.3ps RMS typical jitter (including spurs),12kHz to 20MHz
Operating modes: locked to input signal, holdover and free-run
Initial holdover accuracy of ±50ppb
Accepts two LVPECL, LVDS, LVHSTL, HCSL or LVCMOS
input clocks
Accepts frequencies ranging from 8kHz up to 875MHz
Auto and manual input clock selection with hitless switching
Clock input monitoring, including support for gapped clocks
Phase-Slope Limiting and Fully Hitless Switching options to
control output phase transients
Operates from a 10MHz to 40MHz fundamental-mode crystal
Generates 8 LVPECL/LVDS/HCSL or 16 LVCMOS output clocks
Output frequencies ranging from 8kHz up to 1.0GHz (diff)
Output frequencies ranging from 8kHz to 250MHz (LVCMOS)
Four General Purpose I/O pins with optional support for status &
control:
Four Output Enable control inputs may be mapped to any of the
eight outputs
Lock, Holdover & Loss-of-Signal status outputs
Open-drain Interrupt pin
Nine programmable PLL loop bandwidth settings from 1.4Hz to
360Hz.
Optional Fast Lock function
Programmable output phase delays in steps as small as 16ps
Register programmable through I2C or via external I2C EEPROM
Bypass clock paths for system tests
Power supply modes
VCC / VCCA / VCCO
3.3V / 3.3V / 3.3V
3.3V / 3.3V / 2.5V
3.3V / 3.3V / 1.8V (LVCMOS)
2.5V / 2.5V / 3.3V
2.5V / 2.5V / 2.5V
2.5V / 2.5V / 1.8V (LVCMOS)
-40°C to 85°C ambient operating temperature
Package: 56QFN, lead-free RoHs (6)
©2016 Integrated Device Technology, Inc.
1
Revision 5, October 26, 2016

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8T49N285 pdf, ピン配列
Pin Assignment
nQ1
Q1
VCCO1
nRST
nQ0
Q0
VCCO0
nINT
VCCA
CAP_REF
CAP
PLL_BYP
VCCA
VCCA
42 41 40 39 38 37 36 35 34 33 32 31 30 29
43 28
44 27
45 26
46 25
47 24
48 23
49 22
50
8T49N285
21
51 20
52 19
53 18
54 17
55 16
56 15
1 2 3 4 5 6 7 8 9 10 11 12 13 14
nQ2
Q2
VCCO2
GPIO[0]
nQ3
Q3
VCCO3
GPIO[1]
VCCA
RESERVED
RESERVED
VCC
VCCA
VCCA
56-pin, 8mm x 8mm VFQFN Package
Figure 2. Pin-out Drawing
8T49N285 Datasheet
©2016 Integrated Device Technology, Inc.
3
Revision 5, October 26, 2016


3Pages


8T49N285 電子部品, 半導体
8T49N285 Datasheet
Principles of Operation
The 8T49N285 can be locked to either of the input clocks and
generate a wide range of synchronized output clocks.
It could be used for example in either the transmit or receive path of
Synchronous Ethernet equipment.
The 8T49N285 accepts up to two differential input clocks ranging
from 8kHz up to 875MHz. It generates up to 8 output clocks ranging
from 8kHz up to 1.0GHz.
The PLL path within the 8T49N285 supports three states: Lock,
Holdover and Free-run. Lock & holdover status may be monitored on
register bits and pins. The PLL also supports automatic and manual
hitless reference switching. In the locked state, the PLL locks to a
valid clock input and its output clocks have a frequency accuracy
equal to the frequency accuracy of the input clock. In the Holdover
state, the PLL will output a clock which is based on the selected
holdover behavior. The PLL within the 8T49N285 has an initial
holdover frequency offset of ±50ppb. In the Free-run state, the PLL
outputs a clock with the same frequency accuracy as the external
crystal.
Upon power up, the PLL will enter Free-run state, in this state it
generates output clocks with the same frequency accuracy as the
external crystal. The 8T49N285 continuously monitors each input for
activity (signal transitions).
In automatic reference switching, when an input clock has been
validated the PLL will transition to the locked state. If the selected
input clock fails and there are no other valid input clocks, the PLL will
quickly detect that and go into holdover. In the Holdover state, the
PLL will output a clock which is based on the selected holdover
behavior. If the selected input clock fails and another input clock is
available then the 8T49N285 will hitlessly switch to that input clock.
The reference switch can be either revertive or non-revertive.
The device supports conversion of any input frequencies to three
different, independent output frequencies on the Q0 and Q[2:3]
outputs. Additionally, a further five output frequencies may be
generated that are integer-related to the three independent
frequencies. These additional five frequencies are on the Q1 and
Q[4:7] outputs.
The 8T49N285 has a programmable loop bandwidth from 1.4Hz to
360Hz.
The device monitors all input clocks and generates an alarm when an
input clock failure is detected.
The device supports programmable individual output phase
adjustments in order to allow control of input to output phase
adjustments and output to output phase alignment.
The device is programmable through an I2C and may also
autonomously read its register settings from an internal One-Time
Programmable (OTP) memory or an external serial I2C EEPROM.
Crystal Input
The crystal input on the 8T49N285 is capable of being driven by a
parallel-resonant, fundamental mode crystal with a frequency range
of 10MHz - 40MHz.
The oscillator input also supports being driven by a single-ended
crystal oscillator or reference clock.
The initial holdover frequency offset is set by the device, but the long
term drift depends on the quality of the crystal or oscillator attached
to this port.
Bypass Path
For system test purposes, the PLL may be bypassed. When
PLL_BYP is asserted the CLK0 input reference will be presented to
the Q4 output dividers and the CLK1 Input reference will be
presented to the Q5 output dividers.
Additionally, CLK0 or CLK1 may be used as a clock source for the
output dividers of Q[4:7]. This may only be done for input frequencies
of 250MHz or less.
Input Clock Selection
The 8T49N285 accepts up to two input clocks with frequencies
ranging from 8kHz up to 875MHz. Each input can accept LVPECL,
LVDS, LVHSTL, HCSL or LVCMOS inputs using 1.8V, 2.5V or 3.3V
logic levels. To use LVCMOS inputs, refer to the Application Note,
“Wiring the Differential Input to Accept Single-Ended Levels” for
biasing instructions.
In Manual mode, only one of the inputs may be chosen and if that
input fails the PLL will enter holdover.
Manual mode may be operated by directly selecting the desired input
reference in the REFSEL register field. It may also operate via
pin-selection of the desired input clock by selecting that mode in the
REFSEL register field. In that case, GPIO[2] must be used as a Clock
Select input (CSEL). CSEL = 0 will select the CLK0 input and
CSEL = 1 will select the CLK1 input.
In addition, the crystal frequency may be passed directly to the output
dividers for Q[4:7] to use as a reference.
Inputs do not support transmission of spread-spectrum clocking
sources. Since this family is intended for high-performance
applications, it will assume input reference sources to have stabilities
of +100ppm or better, except where gapped clock inputs are used.
If the PLL is working in automatic mode, then each of the input
reference sources is assigned a priority of 1-2. At power-up or if the
currently selected input reference fails, the PLL will switch to the
highest priority input reference that is valid at that time (see “Input
Clock Monitor”section for details).
Automatic mode has two sub-options: revertive or non-revertive. In
revertive mode, the PLL will switch to a reference with a higher
priority setting whenever one becomes valid. In non-revertive mode
the PLL remains with the currently selected source as long as it
remains valid.
The clock input selection is based on the input clock priority set by
the Clock Input Priority control registers. It is recommended that all
input references be given different priority settings in the Clock Input
Priority control register.
©2016 Integrated Device Technology, Inc.
6
Revision 5, October 26, 2016

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