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PDF 8T49N012 Data sheet ( 特性 )

部品番号 8T49N012
部品説明 LVPECL/LVCMOS Clock Generator
メーカ Integrated Device Technology
ロゴ Integrated Device Technology ロゴ 

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8T49N012 Datasheet, 8T49N012 PDF,ピン配置, 機能
FemtoClock® NG Crystal-to-3.3V, 2.5V
LVPECL/LVCMOS Clock Generator with
Fanout Buffer
8T49N012
DATA SHEET
General Description
The 8T49N012 is a high performance Clock Generator with
selectable LVPECL or Single-ended outputs. The 8T49N012 can
generate selectable frequencies from a crystal or a single-ended
reference clock. The frequency is selected from the Frequency
Selection Table.
Excellent phase noise performance is maintained with IDT’s Fourth
Generation FemtoClock® NG PLL technology.
Pin Assignment
SE
VCC
XTAL_SEL
PS_SEL
VCCA
VEE
NA_DIV1
NA_DIV0
VCC_X
XTAL_OUT
XTAL_IN
VEE
CLK_IN
nOE_B
56 55 54 53 52 51 50 49 48 47 46 45 44 43
1 42
2 41
3 40
4 39
5 38
6 37
7
8T49N012
36
8 35
9 34
10 33
11 32
12 31
13 30
14 29
15 16 17 18 19 20 21 22 23 24 25 26 27 28
QC0
nQC0
QC1
nQC1
VCCO_C
QC2
nQC2
VEE
QC3
nQC3
QC4
nQC4
QC5
nQC5
Features
• Fourth Generation FemtoClock NG PLL technology
• Three differential output banks:
Bank A: selectable between four pairs of LVPECL or four pairs
of complementary LVCMOS/LVTTL outputs
Bank B: two pairs of LVPECL outputs
Bank C: six pairs of LVPECL outputs
• Selectable clock input or crystal input.
• Supports 25MHz fundamental crystal or 25MHz, 50MHz,
66.67MHz clock input
• Selectable 156.25MHz, 125MHz, 100MHz clock for Bank B and
Bank C outputs
• Selectable 156.25MHz, 125MHz, 100MHz, 250MHz, 312.5MHz,
50MHz, 25MHz, 62.5MHz or 78.125MHz for Bank A outputs
• PLL lock indication (LVCMOS output)
• RMS phase jitter at 156.25MHz (12kHz - 20MHz): 0.199ps (typical)
• Power supply modes:
Core / Output
3.3V / 3.3V
3.3V / 2.5V
2.5V / 2.5V
• -40°C to 85°C ambient operating temperature
• 56-Lead VFQFN
• Lead-free (RoHS 6) packaging
56-Lead VFQFN, 8.0mm x 8.0mm x 0.9mm
8T49N012 REVISION 1 08/21/14
1
©2014 Integrated Device Technology, Inc.

1 Page





8T49N012 pdf, ピン配列
8T49N012 DATA SHEET
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions1
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Name
SE
VCC
XTAL_SEL
PS_SEL
VCCA
VEE
NA_DIV1
NA_DIV0
VCC_X
XTAL_OUT
XTAL_IN
VEE
CLK_IN
nOE_B
nc
LOCK
FB_DIV
RESERVED
VCC
NB_DIV
VEE
nQB1
QB1
nQB0
QB0
VCCO_B
NC_DIV
VCCO_C
nQC5
QC5
Type
Input
Pulldown
Power
Input
Pulldown
Input
Power
Power
Input
Pulldown
Pulldown
Input
Power
O/I
O/I
Power
Input
Input
unused
Output
Pulldown
Pulldown
Pulldown
Input
Reserve
Power
Input
Power
Output
Output
Output
Output
Power
Input
Power
Output
Output
Pulldown
Pulldown
Pulldown
Description
Select pin for Bank A outputs. LVCMOS/LVTTL interface levels.
See the Function Configuration Tables section.
Core power supply pins.
Select reference source between the crystal or input clock. LVCMOS/
LVTTL interface levels. See the Function Configuration Tables section.
Pre scale divider selection. LVCMOS/LVTTL interface levels.
See the Function Configuration Tables section.
Analog supply for VCO.
Negative power supply pin.
Select output frequency for Bank A outputs. LVCMOS/LVTTL interface
levels. See the Function Configuration Tables section.
Select output frequency for Bank A outputs. LVCMOS/LVTTL interface
levels. See the Function Configuration Tables section.
Crystal oscillator power supply pin.
Crystal oscillator interface output.
Crystal oscillator interface input.
Negative power supply pin.
Single-ended input clock. LVCMOS/LVTTL interface levels.
Output enable for Bank B outputs. LVCMOS/LVTTL interface levels.
See the Function Configuration Tables section.
No connect pin.
PLL lock indicator. Logic High indicates PLL is locked. LVCMOS/LVTTL
interface levels. See the Function Configuration Tables section.
Feedback divider selection. LVCMOS/LVTTL interface levels.
See the Function Configuration Tables section.
Reserve pin. Do not connect.
Core power supply pin.
Select output frequency for Bank B outputs. LVCMOS/LVTTL interface
levels. See the Function Configuration Tables section.
Negative power supply pin.
Differential Bank B outputs. LVPECL interface levels.
Differential Bank B outputs. LVPECL interface levels.
Bank B output power supply pin.
Select output frequency for Bank C outputs. LVCMOS/LVTTL interface
levels. See the Function Configuration Tables section.
Bank C output power supply pin.
Differential Bank C outputs. LVPECL interface levels.
REVISION 1 08/21/14
3 FEMTOCLOCK® NG CRYSTAL-TO-3.3V, 2.5V LVPECL/LVCMOS
CLOCK GENERATOR


3Pages


8T49N012 電子部品, 半導体
8T49N012 DATA SHEET
Table 3H. Bank A Output Divider table
Input
Frequency (MHz)
PS_SEL
25 Low (default)
66.66667
Mid
50 High
FB_DIV
Low (default)
Mid
Low
NA_DIV [1:0]
Low, Low (default)
Low, High
High, Low
High, High
Low, Mid
High, Mid
Mid, Low
Mid, High
Mid, Mid
Low, Low (default)
Low, High
High, Low
High, High
Low, Mid
High, Mid
Mid, Low
Mid, High
Mid, Mid
Low, Low (default)
Low, High
High, Low
High, High
Low, Mid
High, Mid
Mid, Low
Mid, High
Mid, Mid
Bank A
Frequency (MHz)
125
156.25
312.5
100
25
50
250
62.5
78.125
125
156.25
312.5
100
25
50
250
62.5
78.125
125
156.25
312.5
100
25
50
250
62.5
78.125
FEMTOCLOCK® NG CRYSTAL-TO-3.3V, 2.5V LVPECL/LVCMOS
CLOCK GENERATOR
6
REVISION 1 08/21/14

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