8V44N4614 PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 8V44N4614
部品説明 NG Jitter Attenuator and Clock Synthesizer
メーカ Integrated Device Technology
ロゴ Integrated Device Technology ロゴ 

Total 30 pages

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8V44N4614 Datasheet, 8V44N4614 PDF,ピン配置, 機能
FemtoClock® NG Jitter Attenuator and
Clock Synthesizer
General Description
The 8V44N4614 is a FemtoClock® NG Clock Generator. The device
has been designed for frequency generation in high-performance
systems such wireless base-band boards, for instance to drive the
reference clock inputs of processors, PHY, switch and SerDes
devices. The device is very flexible in frequency programming. It
allows to generate the clock frequencies of 156.25MHz, 125MHz,
100MHz and 25MHz individually at three output banks. One output
bank supports configurable LVDS, LVPECL, the other two output
banks support LVCMOS output levels. All outputs are synchronized
on the incident rising edge, regardless of the selected output
frequency. Selective single-ended LVCMOS outputs can be
configured to invert the output phase, effectively forming differential
LVCMOS output pairs for noise reduction. The PLL reference signal
is either a 25MHz, 50MHz, 100MHz or 200MHz differential or
single-ended clock.
The device is optimized to deliver excellent period and cycle-to-cycle
jitter performance, combined with good phase noise performance,
and high power supply noise rejection.
The device is configured through an SPI serial interface. Outputs can
be configured to any of the available output frequencies. Two
hardware pins are available for selecting pre-set output enable/
disable configurations. In each of these pre-set configurations, each
output can be enabled/disabled individually. A separate test mode is
available for an increase or decrease of the output frequencies in
19.53125ppm steps independent on the input frequency. The device
is packaged in a lead-free (RoHS 6) 48-lead VFQFN package. The
extended temperature range supports wireless infrastructure,
telecommunication and networking end equipment requirements.
Clock generator for wireless base-band systems
Drives reference clock inputs of processors, PHY, switch and
SerDes devices
FemtoClock® NG technology
Three low-skew, differential LVDS, LVPECL configurable clock
Ten low-skew, LVCMOS/LVTTL clock outputs
Input: 200MHz, 100MHz, 50MHz, 25MHz single-ended
(LVCMOS) or differential reference clock (LVDS, LVPECL)
Output clocks support 156.25MHz, 125MHz, 100MHz and 25MHz
Individual output disable (high-impedance)
Two sets of output enable configurations
PLL lock detect output
Test mode with frequency margining with 19.53125ppm steps
(range ±507.8125ppm)
LVCMOS (1.8V, JESD8-7A) compatible SPI programming
Cycle-to-cycle jitter: 10ps (typical)
RMS period jitter: 1.6ps (typical)
Phase noise (12kHz - 20MHz): 0.40ps (typical)
3.3V core and output supply
-40°C to +85°C ambient operating temperature
Lead-free (RoHS 6) 48-lead VFQFN packaging
REVISION 1 02/25/15

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NG Jitter Attenuator and Clock Synthesizer

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