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PDF 8T49NS010 Data sheet ( 特性 )

部品番号 8T49NS010
部品説明 Clock Synthesizer and Fanout Buffer/Divider
メーカ Integrated Device Technology
ロゴ Integrated Device Technology ロゴ 

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8T49NS010 Datasheet, 8T49NS010 PDF,ピン配置, 機能
Clock Synthesizer
and Fanout Buffer/Divider
8T49NS010
DATA SHEET
General Description
The 8T49NS010 is a Clock Synthesizer and Fanout Buffer/Divider.
When used with an external crystal, the 8T49NS010 generates high
performance timing geared towards the communications and data-
com markets, especially for applications demanding extremely low
phase noise jitter, such as 10, 40 and 100GE.
The 8T49NS010 provides versatile frequency configurations and
output formats and is optimized to deliver excellent phase noise
performance. The device delivers an optimum combination of high
clock frequency and low phase noise performance, combined with
high power supply noise rejection.
The 8T49NS010 supports two types of output levels. FORMAT #1
Outputs provide an output level with 750mV typical swing, and
requires external DC termination. FORMAT #2 Outputs provide a
similar swing level which does not require DC termination.
The device can be configured through an I2C serial interface and is
offered in a lead-free (RoHS6) 56-pin VFQFN package.
The extended temperature range supports telecommunication and
networking end equipment requirements.
Features
Ten differential outputs
The input operates in full differential mode (LVDS, LVPECL) or
single-ended LVCMOS mode
Can be driven from a crystal or differential clock
Support of output power-down
Excellent clock output phase noise
Offset Output Frequency Single-side Band Phase Noise
100kHz
156.25MHz
-144 dBc/Hz
Phase Noise RMS, 12kHz to 20MHz integration range:
84fs (typical)
LVCMOS compatible I2C serial interface
I2C control inputs are 3.3V tolerant
Full 3.3V supply voltage
Lead-free (RoHS 6) 56-pin VFQFN packaging
-40°C to 85°C ambient operating temperature
Additional Ordering Information
Part/Order Number
Package
8T49NS010-156NLGI
56-pin VFQFN
Output Frequency (MHz)
156.25, 312.5, 625, 1250
8T49NS010 REVISION 1 11/19/14
1 ©2014 Integrated Device Technology, Inc.

1 Page





8T49NS010 pdf, ピン配列
Pin Assignment
8T49NS010 DATA SHEET
VSS_I2C
SCLK
SDATA
nCLK_IN
CLK_IN
VDD_I2C
REF_SEL
CAP
VDD_XTAL
XTAL_IN
XTAL_OUT
VSS_XTAL
FB_SEL
OUTPUT TYPE
42 41 40 39 38 37 36 35 34 33 32 31 30 29
43 28
44 27
45 26
46 25
47 24
48 23
49 8T49NS010 22
50 21
51 20
52 19
53 18
54 17
55 16
56 15
1 2 3 4 5 6 7 8 9 10 11 12 13 14
VDD_A
VEE_A
Loop_Filter
Loop_Filter_R
BIAS_CAPR
BIAS_CAP
VDD_A2
VSS_A2
VDD_LC_IN
VSS_FB
VDD_FB
VSS_CP
CP
VDD_CP
56-pin 8mm x 8mm VFQFN Package
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions1
Number
1
2
Name
QCLK0
nQCLK0
Type
Output
Output
Description
Differential clock output pair. FORMAT #1 or FORMAT #2 output levels.
3
VDD_CLK
Power
4
QCLK1
Output
5
nQCLK1
Output
Power Supply Voltage (3.3V).
Differential clock output pair. FORMAT #1 or FORMAT #2 output levels.
6
QCLK2
Output
7
nQCLK2
Output
Differential clock output pair. FORMAT #1 or FORMAT #2 output levels.
8
VDD_CLK
Power
9
QCLK3
Output
10
nQCLK3
Output
Power Supply Voltage (3.3V).
Differential clock output pair. FORMAT #1 or FORMAT #2 output levels.
11
QCLK4
Output
12
nQCLK4
Output
Differential clock output pair. FORMAT #1 or FORMAT #2 output levels.
REVISION 1 11/19/14
3 CLOCK SYNTHESIZER AND FANOUT BUFFER/DIVIDER


3Pages


8T49NS010 電子部品, 半導体
8T49NS010 DATA SHEET
Principles of Operation
Depending on the input used, the 8T49NS010’s low phase noise
integer-N PLL can multiply the reference to 2400MHz to 2500MHz.
The device offers ten clock outputs (QCLK[9:0]/nQCLK[9:0]). Each
output can be disabled individually through registers. With ÷2, ÷4, ÷8
and ÷16 values one can get output frequencies of 156.25MHz,
312.5MHz, 625MHz and 1250MHz when driven from a 25MHz input,
for example. Table 4A to Table 4C show functions of the hardware pin
settings. The input select pin REF_SEL will choose either XTAL input
or CLK_IN input and this pin also set the pre-divider PRE to either x2
or ÷1. Feedback divider FB_SEL pin will set the feedback divider to
either ÷50, ÷25. The VCO of this device is 2.5GHz. The feedback
divider should be properly set to assure the PLL lock for
VCO=2.5GHz. N1 and N0 are pins for output frequency divider
setting. Table 4D provide some examples of setting output to
156.25MHz. N1 and N0 can be set for other output frequencies.
Additional divider values are available through registers that can be
programmed with I2C interface. Table 4C lists the frequencies
available with select pins on the device, while Table 4E lists all
available divider configurations via I2C.
The 8T49NS010 operates over the industrial temperature range of
-40°C to +85°C.
The outputs are compatible with LVPECL-type logic levels, described
as FORMAT #1 or FORMAT #2 (see Termination for QCLKn Outputs)
and the DC characteristics for these two formats in the DC Electrical
Characteristics (Table 6D and Table 6E). Table 4C, below, shows an
example using a 2500MHz VCO frequency input with the selected
output dividers shown, resulting in the listed output frequencies. The
output divider N can also be set via internal registers. The
configuration and re-configuration of any of the output dividers
requires an I2C write sequence.
Each QCLK output can be individually disabled through an I2C
command.
Table 4A. REF_SEL Input Pin Setting
REF_SEL
INPUT
÷PRE
0 (Default)
XTAL_IN
X2
1
CLK_IN
÷1
Table 4B. FBSEL Feedback divider Pin Setting
FB_SEL
0 (Default)
Feedback Divider
÷50
1 ÷25
Table 4C. Hardware Pins N1 and N0 Output Frequency 
Divider Setting
N[1:0]
00
Output Divider N
÷2
Output Frequency
(FVCO = 2500MHz)
1250MHz
01 ÷4
625MHz
10 ÷8
312.5MHz
11 (Default)
÷16
156.25MHz
Table 4D. Hardware Pin Setting Examples
Input
(MHz)
Output
REF_SEL FB_SEL N[1:0] (VCO=2500MHz) Comments
XTAL_IN=25 0, [PRE=x2] 0[÷50] 11[÷16]
XTAL_IN=50 0, [PRE=x2] 1[÷25] 11[÷16]
156.25MHz
156.25MHz
Default
Recommended
CLK_IN=50 1, [PRE=÷1] 0[÷50] 11[÷16]
CLK_IN=100 1, [PRE=÷1] 1[÷25] 11[÷16]
156.25MHz
156.25MHz
Table 4E. Output Frequency Divider Settings, I2C Only
N[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
Divider Value
÷1
÷2
÷3
÷4
÷5
÷6
÷8
÷10
÷12
÷16
÷20
÷24
Reference Clock Inputs
The 8T49NS010 features one differential reference clock input
(CLK_IN, nCLK_IN) and a crystal input. This input can be configured
to operate in full differential mode (LVDS or LVPECL) or single-ended
3.3V CMOS mode.
(The input signal frequency is divided down through a prescaler
function (PV).)
The reference input divider (PV) provides division ratios as shown in
Table 4F.
This divider setting may be adjusted via the PV bit in the Reference
Control Register.
Table 4F. Available Pre-Divider Settings (PV), I2C Only
Register Bits PDIV[1:0]
00
01
10
11
PV Divider Settings
x2
÷1
÷2
÷4
CLOCK SYNTHESIZER AND FANOUT BUFFER/DIVIDER
6
REVISION 1 11/19/14

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