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5P49V5944 の電気的特性と機能

5P49V5944のメーカーはIntegrated Device Technologyです、この部品の機能は「Programmable Clock Generator」です。


製品の詳細 ( Datasheet PDF )

部品番号 5P49V5944
部品説明 Programmable Clock Generator
メーカ Integrated Device Technology
ロゴ Integrated Device Technology ロゴ 




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5P49V5944 Datasheet, 5P49V5944 PDF,ピン配置, 機能
Programmable Clock Generator
5P49V5944
DATASHEET
Description
The 5P49V5944 is a programmable clock generator intended
for high performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I2C
interface. This is IDTs fifth generation of programmable clock
technology (VersaClock® 5).
The frequencies are generated from a single reference clock.
The input reference can be either a crystal or an LVCMOS
reference clock.
Two select pins allow up to 4 different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for
different operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or
system production margin testing.
The device may be configured to use one of two I2C
addresses to allow multiple devices to be used in a system.
Pin Assignment
XOUT
XIN/REF
VDDA
GND
SD/OE
20 19 18 17 16
1 15
2 14
3
EPAD
13
4 12
5 11
6 7 8 9 10
VDDO1
OUT1
OUT1B
GND
GND
20-pin VFQFPN
Features
Generates up to two independent output frequencies
High performance, low phase noise PLL, <0.7 ps RMS
typical phase jitter on outputs:
– PCIe Gen1, 2, 3 compliant clock capability
– USB 3.0 compliant clock capability
– 1 GbE and 10 GbE
Two fractional output dividers (FODs)
Independent Spread Spectrum capability on each output
pair
Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
I2C serial programming interface
One reference LVCMOS output clock
Two universal output pairs:
– Each configurable as one differential output pair or two
LVCMOS outputs
I/O Standards:
– Single-ended I/Os: 1.8V to 3.3V LVCMOS
– Differential I/Os - LVPECL, LVDS and HCSL
Input frequency ranges:
– LVCMOS Reference Clock Input (XIN/REF) – 1MHz
to 200MHz
– Crystal frequency range: 8MHz to 40MHz
Output frequency ranges:
– LVCMOS Clock Outputs – 1MHz to 200MHz
– LVDS, LVPECL, HCSL Differential Clock Outputs –
1MHz to 350MHz
Individually selectable output voltage (1.8V, 2.5V, 3.3V) for
each output pair
Programmable loop bandwidth
Programmable output to output skew
Programmable slew rate control
Programmable crystal load capacitance
Individual output enable/disable
Power-down mode
1.8V, 2.5V or 3.3V core VDDD, VDDA
Available in 20-pin VFQFPN 3mm x 3mm package
-40° to +85°C industrial temperature operation
5P49V5944 NOVEMBER 11, 2016
1 ©2016 Integrated Device Technology, Inc.

1 Page





5P49V5944 pdf, ピン配列
5P49V5944 DATASHEET
Table 1: Pin Descriptions
Number
1
Name
XOUT
Type
Input
2
XIN/REF
Input
3
VDDA
Power
4
GND
Power
5
SD/OE
Input
Pull-down
6
SEL1/SDA
Input
Pull-down
7
SEL0/SCL
Input
Pull-down
8
VDDO2
Power
9
OUT2
Output
10
OUT2B
Output
11
GND
Power
12
GND
Power
13
OUT1B
Output
14
OUT1
Output
15
VDDO1
Power
16
GND
Power
17
VDDD
Power
18
GND
Power
19
VDDO0
Power
20 OUT0_SELB_I2C Input/Output Pull-down
ePAD
Description
Crystal Oscillator interface output.
Crystal Oscillator interface input, or single-ended LVCMOS clock input. Ensure
that the input voltage is 1.2V max. Refer to the section “Overdriving the XIN/REF
Interface”.
Analog functions power supply pin. Connect to 1.8V to 3.3V. VDDA and VDDD
should have the same voltage applied.
Connect to ground.
Enables/disables the outputs (OE) or powers down the chip (SD). The SH bit
controls the configuration of the SD/OE pin. The SH bit needs to be high for
SD/OE pin to be configured as SD. The SP bit (0x02) controls the polarity of the
signal to be either active HIGH or LOW only when pin is configured as OE
(Default is active LOW.) Weak internal pull down resistor. When configured as
SD, device is shut down, differential outputs are driven high/low, and the single-
ended LVCMOS outputs are driven low. When configured as OE, and outputs are
disabled, the outputs can be selected to be tri-stated or driven high/low,
depending on the programming bits as shown in the SD/OE Pin Function Truth
table.
Configuration select pin, or I2C SDA input as selected by OUT0_SEL_I2CB.
Weak internal pull down resistor.
Configuration select pin, or I2C SCL input as selected by OUT0_SEL_I2CB.
Weak internal pull down resistor.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for
OUT2/OUT2B.
Output Clock 2. Please refer to the Output Drivers section for more details.
Complementary Output Clock 2. Please refer to the Output Drivers section for
more details.
Connect to ground.
Connect to ground.
Complementary Output Clock 1. Please refer to the Output Drivers section for
more details.
Output Clock 1. Please refer to the Output Drivers section for more details.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for
OUT1/OUT1B.
Connect to ground.
Digital functions power supply pin. Connect to 1.8 to 3.3V. VDDA and VDDB
should have the same voltage applied.
Connect to ground.
Power supply pin for OUT0_SEL_I2CB. Connect to 1.8 to 3.3V. Sets output
voltage levels for OUT0.
Latched input/LVCMOS Output. At power up, the voltage at the pin
OUT0_SEL_I2CB is latched by the part and used to select the state of pins 8
and 9. If a weak pull up (10Kohms) is placed on OUT0_SEL_I2CB, pins 8 and 9
will be configured as hardware select pins, SEL1 and SEL0. If a weak pull down
(10Kohms) is placed on OUT0_SEL_I2CB or it is left floating, pins 8 and 9 will
act as the SDA and SCL pins of an I2C interface. After power up, the pin acts as
a LVCMOS reference output.
Connect to ground pad.
NOVEMBER 11, 2016
3 PROGRAMMABLE CLOCK GENERATOR


3Pages


5P49V5944 電子部品, 半導体
5P49V5944 DATASHEET
OTP Interface
The 5P49V5944 can also store its configuration in an internal
OTP. The contents of the device's internal programming
registers can be saved to the OTP by setting burn_start
(W114[3]) to high and can be loaded back to the internal
programming registers by setting usr_rd_start(W114[0]) to
high.
To initiate a save or restore using I2C, only two bytes are
transferred. The Device Address is issued with the read/write
bit set to “0”, followed by the appropriate command code. The
save or restore instruction executes after the STOP condition
is issued by the Master, during which time the 5P49V5944 will
not generate Acknowledge bits. The 5P49V5944 will
acknowledge the instructions after it has completed execution
of them. During that time, the I2C bus should be interpreted as
busy by all other users of the bus.
On power-up of the 5P49V5944, an automatic restore is
performed to load the OTP contents into the internal
programming registers. The 5P49V5944 will be ready to
accept a programming instruction once it acknowledges its
7-bit I2C address.
Availability of Primary and Secondary I2C addresses to allow
programming for multiple devices in a system. The I2C slave
address can be changed from the default 0xD4 to 0xD0 by
programming the I2C_ADDR bit D0. VersaClock 5
Programming Guide provides detailed I2C programming
guidelines and register map.
SD/OE Pin Function
The polarity of the SD/OE signal pin can be programmed to be
either active HIGH or LOW with the SP bit (W16[1]). When SP
is “0” (default), the pin becomes active LOW and when SP is
“1”, the pin becomes active HIGH. The SD/OE pin can be
configured as either to shutdown the PLL or to enable/disable
the outputs. The SH bit controls the configuration of the
SD/OE pin The SH bit needs to be high for SD/OE pin to be
configured as SD.
SP
SD/OE Input
SH
OEn
Global Shutdown
OSn
OUTn
When configured as SD, device is shut down, differential
outputs are driven High/low, and the single-ended LVCMOS
outputs are driven low. When configured as OE, and outputs
are disabled, the outputs are driven high/low.
Table 4: SD/OE Pin Function Truth Table
SH bit SP bit OSn bit OEn bit SD/OE
OUTn
00
0
x
x Tri-state2
00
1
0 x Output active
00
1
1 0 Output active
00
1
1 1 Output driven High Low
01
0
x
x Tri-state2
01
1
0 x Output active
01
1
1 0 Output driven High Low
01
1
1 1 Output active
10
0
x
0 Tri-state2
10
1
0 0 Output active
10
1
1 0 Output active
11
0
x
0 Tri-state2
11
1
0 0 Output active
11
1
1 0 Output driven High Low
1x
x
x 1 Output driven High Low 1
Note 1 : Global Shutdown
Note 2 : Tri-state regardless of OEn bits
Output Divides
Each output divide block has a synchronizing POR pulse to
provide startup alignment between outputs divides. This
allows alignment of outputs for low skew performance. This
low skew would also be realized between outputs that are
both integer divides from the VCO frequency. This phase
alignment works when using configuration with SEL1, SEL0.
For I2C programming, I2C reset is required.
An output divide bypass mode (divide by 1) will also be
provided, to allow multiple buffered reference outputs.
Each of the two output divides are comprised of a 12 bit
integer counter, and a 24 bit fractional counter. The output
divide can operate in integer divide only mode for improved
performance, or utilize the fractional counters to generate a
clock frequency accurate to 50 ppb.
Each of the output divides also have structures capable of
independently generating spread spectrum modulation on the
frequency output.
The Output Divide also has the capability to apply a spread
modulation to the output frequency. Independent of output
frequency, a triangle wave modulation between 30 and 63kHz
may be generated.
For all outputs, there is a bypass mode, to allow the output to
behave as a buffered copy of the input.
PROGRAMMABLE CLOCK GENERATOR
6
NOVEMBER 11, 2016

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部品番号部品説明メーカ
5P49V5943

Programmable Clock Generator

Integrated Device Technology
Integrated Device Technology
5P49V5944

Programmable Clock Generator

Integrated Device Technology
Integrated Device Technology


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