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SL23EP09 の電気的特性と機能

SL23EP09のメーカーはSilicon Laboratoriesです、この部品の機能は「Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer」です。


製品の詳細 ( Datasheet PDF )

部品番号 SL23EP09
部品説明 Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer
メーカ Silicon Laboratories
ロゴ Silicon Laboratories ロゴ 




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SL23EP09 Datasheet, SL23EP09 PDF,ピン配置, 機能
SL23EP09
Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB)
Key Features
10 to 220 MHz operating frequency range
Low output clock skew: 45ps-typ
Low output clock jitter:
50 ps-typ cycle-to-cycle jitter
20 ps-typ period jitter
Low part-to-part output skew: 90 ps-typ
Wide 2.5 V to 3.3 V power supply range
Low power dissipation:
26 mA-max at 66 MHz and VDD=3.3 V
24 mA-max at 66 MHz and VDD=2.5V
One input drives 9 outputs organized as 4+4+1
Select mode to bypass PLL or tri-state outputs
SpreadThru™ PLL that allows use of SSCG
Standard and High-Drive options
Available in 16-pin SOIC and TSSOP packages
Available in Commercial and Industrial grades
Applications
Printers, MFPs and Digital Copiers
PCs and Work Stations
Routers, Switchers and Servers
Digital Embeded Systems
Block Diagram
Description
The SL23EP09 is a low skew, low jitter and low power Zero
Delay Buffer (ZDB) designed to produce up to nine (9) clock
outputs from one (1) reference input clock, for high speed
clock distribution applications.
The product has an on-chip PLL which locks to the input
clock at CLKIN and receives its feedback internally from the
CLKOUT pin.
The SL23EP09 has two (2) clock driver banks each with four
(4) clock outputs. These outputs are controlled by two (2)
select input pins S1 and S2. When only four (4) outputs are
needed, four (4) bank-B output clock buffers can be tri-stated
to reduce power dissipation and jitter. The select inputs can
also be used to tri-state both banks A and B or drive them
directly from the input bypassing the PLL and making the
product behave like a Non-Zero Delay Buffer (NZDB).
The high-drive version operates up to 220MHz and 200MHz
at 3.3V and 2.5V power supplies respectively.
Benefits
Up to nine (9) distribution of input clock
Standard and High-Dirive levels to control impedance
level, frequency range and EMI
Low power dissipation, jitter and skew
Low cost
CLKIN
Low Power and
Low Jitter
PLL
MUX
S2
Input Selection
Decoding Logic
S1
2
VDD
2
GND
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Rev 2.0, May 12, 2008
2400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500
1+(512) 416-9669
Page 1 of 14
www.silabs.com

1 Page





SL23EP09 pdf, ピン配列
SL23EP09
General Description
The SL23EP09 is a low skew, low jitter Zero Delay Buffer
with very low operating current.
The product includes an on-chip high performance PLL that
locks into the input reference clock and produces nine (9)
output clock drivers tracking the input reference clock for
systems requiring clock distribution.
in addition to CLKOUT that is used for internal PLL
feedback, there are two (2) banks with four (4) outputs in
each bank, bringing the number of total available output
clocks to nine (9).
Input and output Frequency Range
The input and output frequency range is the same. But, it
depends on VDD and drive levels as given in the below
Table 1.
VDD(V) Drive Min(MHz) Max(MHz)
3.3 HIGH
10
220
3.3 STD 10
200
2.5 HIGH
10
180
2.5 STD 10
167
Table 1. Input/Output Frequency Range
If the input clock frequency is DC (GND to VDD), this is
detected by an input frequency detection circuitry and all
nine (9) clock outputs are forced to Hi-Z. The PLL is
shutdown to save power. In this shutdown state, the product
draws less than 12 μA supply current.
Select Input Control
The SL23EP09 provides two (2) input select control pins
called S1 and S2. This feature enables users to selects
various states of output clock banks-A and bank-B, output
source and PLL shutdown features as shown in the Table 2.
The S1 (Pin-9) and S2 (Pin-8) inputs include 250 kΩ weak
pull-up resistors to VDD.
PLL Bypass Mode
If the S2 and S1 pins are logic High(1) and Low(0)
respectively, the on-chip PLL is shutdown and bypassed,
and all the nine output clocks bank A, bank B and CLKOUT
clocks are driven directly from the reference input clock. In
this operation mode SL23EP09 works like a non-ZDB fanout
buffer.
High and Low-Drive Product Options
The SL23EP09 is offered with High-Drive “-1H” and
Standard-Drive “-1” options. These drive options enable the
users to control load levels, frequency range and EMI
control. Refer to the AC electrical tables for the details.
Skew and Zero Delay
All outputs should drive the similar load to achieve output-to-
output skew and input-to-output specifications given in the
AC electrical tables. However, Zero delay between input
and outputs can be adjusted by changing the loading of
CLKOUT relative to the banks A and B clocks since
CLKOUT is the feedback to the PLL.
SpreadThruFeature
If a Spread Spectrum Clock (SSC) were to be used as an
input clock, the SL23EP09 is designed to pass the
modulated Spread Spectrum Clock (SSC) signal from its
reference input to the output clocks. The same spread
characteristics at the input are passed through the PLL and
drivers without any degradation in spread percent (%),
spread profile and modulation frequency
Power Supply Range (VDD)
The SL23EP09 is designed to operate in a wide power
supply range from 2.3V (Min) to 3.6V (Max). An internal on-
chip voltage regulator is used to supply PLL constant power
supply of 1.8V, leading to a consistent and stable PLL
electrical performance in terms of skew, jitter and power
dissipation. Contact SLI for 1.8V power supply version ZDB
called SL23EPL09.
Rev 2.0, May 12, 2008
Page 3 of 14


3Pages


SL23EP09 電子部品, 半導体
SL23EP09
Operating Conditions: Unless Otherwise Stated VDD=2.3V to 3.6V and for Both C and I Grades
Symbol
Description
Condition
Min.
Max.
VDD3.3 3.3V Supply Voltage
3.3V+/-10%
3.0 3.6
VDD2.5 2.5V Supply Voltage
2.5V+/-10%
2.3 2.7
TA Operating Temperature(Ambient) Commercial
0 70
Industrial
–40 85
CLOAD Load Capacitance
<220 MHz, 3.3V with High Drive
– 15
<200 MHz, 3.3V with Standard drive
15
<180 MHz, 2.5V with High Drive
– 15
<167 MHz, 2.5V with Standard drive
15
<200 MHz, 3.3V with High Drive
– 22
<180 MHz, 3.3V with Standard drive
22
<167 MHz, 2.5V with High Drive
– 22
<134 MHz, 2.5V with Standard drive
22
<133 MHz, 3.3V with High Drive
– 30
<100 MHz, 3.3V with Standard drive
30
<80 MHz, 2.5V with High Drive
– 30
<67 MHz, 2.5V with Standard drive
– 30
CIN Input Capacitance
S1, S2 and CLKIN pins
–5
Pull-up and Pull-down Resistors
RPU/D
CLBW Closed-loop bandwidth
Pins-12/3/6/7/8/9/10/11/14/15/16
250kΩ-typ
3.3V, (typical)
175 325
1.2
2.5V, (typical)
0.8
ZOUT Output Impedance
3.3V, (typical), High drive
29
3.3V, (typical), Standard drive
41
2.5V, (typical), High drive
37
2.5V, (typical), Standard drive
41
Unit
V
V
°C
°C
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
MHz
MHz
Rev 2.0, May 12, 2008
Page 6 of 14

6 Page



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