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PDF SL23EP08 Data sheet ( Hoja de datos )
| Número de pieza | SL23EP08 | |
| Descripción | Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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SL23EP08
Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB)
Key Features
• 10 to 220 MHz operating frequency range
• Low output clock skew: 45ps-typ
• Low output clock jitter:
25 ps-typ cycle-to-cycle jitter
15 ps-typ period jitter
• Low part-to-part output skew: 90 ps-typ
• Wide 2.5 V to 3.3 V power supply range
• Low power dissipation:
20 mA-max at 66 MHz and VDD=3.3 V
18 mA-max at 66 MHz and VDD=2.5V
• One input drives 8 outputs
• Multiple configurations and drive options
• Select mode to bypass PLL or tri-state outputs
• SpreadThru™ PLL that allows use of SSCG
• Available in 16-pin SOIC and TSSOP packages
• Available in Commercial and Industrial grades
Applications
• Printers, MFPs and Digital Copiers
• PCs and Work Stations
• Routers, Switchers and Servers
• Datacom and Telecom
• High-SpeedDigital Embeded Systems
Block Diagram
Description
The SL23EP08 is a low skew, low jitter and low power Zero
Delay Buffer (ZDB) designed to produce up to nine (9) clock
outputs from one (1) reference input clock, for high speed
clock distribution applications.
The product has an on-chip PLL and a feedback pin (FBK)
which can be used to obtain feedback from any one of the
output clocks. The SL23EP08 has two (2) clock driver banks
each with four (4) clock outputs. These outputs are controlled
by two (2) select input pins S1 and S2. When only four (4)
outputs are needed, four (4) bank-B output clock buffers can
be tri-stated to reduce power dissipation and jitter. The select
inputs can also be used to tri-state both banks A and B or
drive them directly from the input bypassing the PLL and
making the product behave like a Non-Zero Delay Buffer
(NZDB). The product also offers various 1X, 2X and 4X
frequency options at the output clocks. Refer to the “Product
Configuration Table” for the details.
The high-drive version operates up to 220MHz and 200MHz at
3.3V and 2.5V power supplies respectively.
Benefits
• Up to eight (8) distribution of input clock
• Standard and High-Dirive levels to control impedance
level, frequency range and EMI
• Low power dissipation, jitter and skew
• Low cost
CLKIN
/2
(Divider for -3 and -4 only)
/2
(Divider for -5H only)
Low Power and
Low Jitter
PLL
MUX
FBK
CLKA1
CLKA2
CLKA3
S2 CLKA4
Input Selection
Decoding Logic
S1
/2
(Divider for -2 and -3 only)
CLKB1
2
VDD
2
GND
CLKB2
CLKB3
CLKB4
Rev 1.0, May 18, 2006
2400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500
1+(512) 416-9669
Page 1 of 15
www.silabs.com
1 page  
SL23EP08
Absolute Maximum Ratings
Description
Supply voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
ESD Rating (Human Body Model)
Condition
In operation, C-Grade
In operation, I-Grade
No power is applied
In operation, power is applied
MIL-STD-883, Method 3015
Min.
– 0.5
– 0.5
0
– 40
– 65
–
–
2000
Max.
4.6
Unit
V
VDD+0.5
V
70 °C
85 °C
150 °C
125 °C
260 °C
–V
Operating Conditions: Unless otherwise stated VDD=2.5V to 3.3V and for both C and I Grades
Symbol Description
Condition
Min.
Max.
VDD3.3 3.3V Supply Voltage
3.3V+/-10%
3.0 3.6
VDD2.5 2.5V Supply Voltage
2.5V+/-10%
2.3 2.7
TA Operating Temperature(Ambient) Commercial
0 70
Industrial
–40 85
CLOAD Load Capacitance
<100 MHz, 3.3V with Standard or High
drive
–
30
<100 MHz, 2.5V with High drive
– 30
<133.3 MHz, 3.3V with Standard or
High drive
– 22
<133.3 MHz, 2.5V with High drive
– 22
<133.3 MHz, 2.5V with Standard drive
–
15
>133.3 MHz, 3.3V with Standard or – 15
High drive
>133.3 MHz, 2.5V with High drive
– 15
CIN Input Capacitance
S1, S2 and CLKIN pins
–5
CLBW Closed-loop bandwidth
3.3V, (typical)
1.2
2.5V, (typical)
0.8
ZOUT Output Impedance
3.3V, (typical), High drive
29
3.3V, (typical), Standard drive
41
2.5V, (typical), High drive
37
2.5V, (typical), Standard drive
41
Unit
V
V
°C
°C
pF
pF
pF
pF
pF
pF
pF
pF
MHz
MHz
Ω
Ω
Ω
Ω
Rev 1.0, May 18, 2006
Page 5 of 15
5 Page 
External Components & Design Considerations
Typical Application Schematic
SL23EP08
CLKIN
1
16
VDD
0.1μF
VDD
0.1μF
42
SL23EP08
3
13
VDD
S1
9
S2 8 5
GND
11
12
GND
FBK
CL-4pF
CLKA1
CL
CLKA2
CLKB4
CL
Comments and Recommendations
Decoupling Capacitor: A decoupling capacitor of 0.1μF must be used between VDD and VSS pins. Place the capacitor on
the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and to the GND via
should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD pin.
Series Termination Resistor: A series termination resistor is recommended if the distance between the output clocks and
the load is over 1 ½ inch. The nominal impedance of the clock outputs is given on the page 4. Place the series termination
resistors as close to the clock outputs as possible.
Zero Delay and Skew Control: All outputs and CLKIN pins should be loaded with the same load to achieve “Zero Delay”
between the CLKIN and the outputs. The CLKOUT pin is connected to CLKIN internally on-chip for feedback to PLL, and
sees an additional 4 pF load with respect to Bank A and B clocks. For applications requiring zero input/output delay, the load
at the all output pins including the CLKOUT pin must be the same. If any delay adjustment is required, the capacitance at the
CLKOUT pin could be increased or decreased to increase or decrease the delay between Bank A and B clocks and CLKIN.
For minimum pin-to-pin skew, the external load at all the Bank A and B clocks must be the same.
Rev 1.0, May 18, 2006
Page 11 of 15
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet SL23EP08.PDF ] | |
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