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PDF ISL6422B Data sheet ( Hoja de datos )
| Número de pieza | ISL6422B | |
| Descripción | Dual Output LNB Supply and Control Voltage Regulator | |
| Fabricantes | Intersil | |
| Logotipo |  |
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Data Sheet
September 8, 2015
ISL6422B
FN6486.2
Dual Output LNB Supply and Control
Voltage Regulator with I2C Interface for
Advanced Satellite Set-Top Box Designs
The ISL6422B is a highly integrated voltage regulator and
interface IC, specifically designed for supplying power and
control signals from advanced satellite set-top box (STB)
modules to the low noise blocks (LNBs) of two antenna
ports. The device is consists of two independent current-
mode boost PWMs and two low-noise linear regulators along
with the circuitry required for 22kHz tone generation,
modulation and I2C device interface. The device makes the
total LNB supply design simple, efficient and compact with
low external component count.
Two independent current-mode boost converters provide the
linear regulators with input voltages that are set to the final
output voltages, plus typically 0.8V to insure minimum power
dissipation across each linear regulator. This maintains
constant voltage drops across each linear pass element
while permitting adequate voltage range for tone injection.
The final regulated output voltages are available at two
output terminals to support simultaneous operation of two
antenna ports for dual tuners. The outputs for each PWM
can be controlled in two ways, full control from I2C using the
VTOP1, VTOP2 and VBOT1, VBOT2 bits or set the I2C to
the lower range ie 13V/14V and switch to higher range ie
18V/19V with the SELVTOP1, SELVTOP2 pins. All the
functions on this IC are controlled via the I2C bus by writing
8 bits words onto the System Registers (SR). The same
register can be read back, and four bits per output will report
the diagnostic status. Separate enable commands sent on the
I2C bus provide independent standby mode control for each
PWM and linear combination, disabling the output into
shutdown mode. Each output channel is capable of providing
750mA of continuous current. The overcurrent limit can be
digitally programmed.
The External modulation input EXTM1, EXTM2 can accept a
modulated DiSEqC command and transfer it symetrically to
the output. Alternatively the EXTM1, EXTM2 pins can be
used to modulate the continuous internal tone.
The FLT pin serves as an interrupt for the processor when any
condition turns OFF the LNB controller (Over- Temperature,
Overcurrent, Disable). The nature of the fault can be read of
the I2C registers.
Features
• Single Chip Power Solution
- True Dual Operation for 2-Tuner/2-Dish Applications
- Both Outputs May be Enabled Simultaneously at
Maximum Power
- Integrated DC/DC Converter and I2C Interface
• Switch-Mode Power Converter for Lowest Dissipation
- Boost PWMs with >92% Efficiency
- Selectable 13.3V or 18.3V Outputs
- Digital Cable Length Compensation (1V)
- I2C and Pin Controllable Output
• Output Back Bias Capability of 28V
• I2C Compatible Interface for Remote Device Control
• Four level Slave Address 0001 00XX
• 2.5V/3.3V/5V Logic Compatible
• External Pins to Toggle Between V and H Polarization
• Built-In Tone Oscillator Factory Trimmed to 22kHz
- Facilitates DiSEqC (EUTELSAT) Encoding
- External Modulation Input
• Internal Over-Temperature Protection and Diagnostics
• Internal OV, UV, Overload and Overtemp Flags (Visible on
I2C)
• FLT Signal
• LNB Short-Circuit Protection and Diagnostics
• QFN and EPTSSOP Packages
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• LNB Power Supply and Control for Satellite Set-Top Box
Ordering Information
PART NUMBER PART
(Note)
MARKING
TEMP.
RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL6422BERZ* 6422B ERZ -20 to +85 40 Ld 6x6 QFN L40.6x6
ISL6422BEVEZ*
(No longer
available,
Recommended
Replacement
ISL6422BERZ)
6422B EVEZ -20 to +85 38 Ld EPTSSOP M38.173B
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas LLC 2007, 2015. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6422B
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V to 18.0V
Logic Input Voltage Range
(SDA, SCL, ADDR0/1, CS1/2, EXTM1/2,
SELVTOP1/, TCAP1/2, TDIN1/2, TXT1/2) . . . . . . . . . -0.5V to 7V
Thermal Information
Thermal Resistance (Typical, Notes 2, 3) JA (°C/W) JC (°C/W)
EPTSSOP Package . . . . . . . . . . . . . . .
29
4
QFN Package. . . . . . . . . . . . . . . . . . . .
34
6
Maximum Junction Temperature (Note 4) . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . -40°C to +150°C
Operating Temperature Range . . . . . . . . . . . . . . . . . -20°C to +85°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
4. The device junction temperature should be kept below +150°C. Thermal shut-down circuitry turns off the device if junction temperature exceeds
+150°C typically.
Electrical Specifications
VCC = 12V, TA = -20°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. EN1/2 = H,
VTOP1/2 = L, VBOT1/2 = L,
software description section
ENT1/2 = L, DCL = L, MSEL1/2
for I2C access to the system.
=
L,
IOUT
=
12mA,
unless
otherwise
noted.
See
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
Operating Supply Voltage Range
8 12 14
V
Standby Supply Current
EN1 = EN2 = L
-
1.5 3.0
mA
Supply Current
IIN EN1 = EN2 = VTOP1 = VTOP2 = VBOT1 =
VBOT2 = ENT1 = ENT2 = H, No Load
-
4.0 8.0
mA
UNDERVOLTAGE LOCKOUT
Start Threshold
7.50 - 7.97
V
Stop Threshold
7.00 - 7.55
V
Start to Stop Hysteresis
350 400 500
mV
SOFT-START
COMP Rise Time (Note 5)
(Note 5)
- 8196 - Cycles
Output Voltage (Note 5)
Line Regulation
Load Regulation
VO1
VO1
VO1
VO1
VO2
VO2
VO2
VO2
DVO1,
DVO2
DVO1,
DVO2
(Refer to Table 11)
(Refer to Table 11)
(Refer to Table 11)
(Refer to Table 11)
(Refer to Table 15)
(Refer to Table 15)
(Refer to Table 15)
(Refer to Table 15)
VIN = 8V to 14V; VO1, VO2 = 13V
VIN = 8V to 14V; VO1, VO2 = 18V
IO = 12mA to 350mA
IO = 12mA to 750mA (Note 6)
13.04
14.02
17.94
19.00
13.04
14.02
17.94
19.00
-
-
-
-
13.30
14.30
18.30
19.30
13.30
14.30
18.30
19.30
4.0
4.0
50
100
13.56
14.58
18.66
19.68
13.56
14.58
18.66
19.68
40.0
60.0
80
200
V
V
V
V
V
V
V
V
mV
mV
mV
mV
5 FN6486.2
September 8, 2015
5 Page 
ISL6422B
be reached early in the soft-start cycle and a 51ms shutdown
timer will be started again. If the fault is still present at the
end of the 51ms, the OLF bit is again set high and the device
once again enters the 900ms OFF time. This dynamic
operation can greatly reduce the power dissipation in a short
circuit condition, still ensuring excellent power-on start-up in
most conditions.
However, there could be some cases in which a highly
capacitive load on the output may cause a difficult start-up
when the dynamic protection is chosen. This can be solved
by initiating any power start-up in static mode (DCL = HIGH)
and then switching to the dynamic mode (DCL = LOW) after
a chosen amount of time. When in static mode, the OLF1,
OLF2 bit goes HIGH when the current clamp limit is reached
and returns LOW at the end of the initial power on soft-start.
In the static mode the output current through the linears is
limitted to 990mA typ.
When a 19.3V line is connected onto a VOUT1 or VOUT2 that
has been set to 13.3V, the linear will then enter a back current
limited state. When a back current of greater that 140mA typ
is sensed at the lower FET of the linear for a period greater
that 2ms, the output is disabled for a period of 50ms and the
BCF1, BCF2 bit are set. If the 19.3V remains connected, the
output will cycle through the ON = 2ms/OFF = 50ms. The
output will return to the setpoint when the fault is removed.
BCF bit is set high during the 50ms OFF period.
Thermal Protection
This IC is protected against overheating. When the junction
temperature exceeds +150°C (typical), the step-up converter
and the linear regulator are shut off and the OTF bit of the
SR is set HIGH. Normal operation is resumed and the OTF
bit is reset LOW when the junction is cooled down to +130°C
(typical).
If a part is repeatedly driven to the over-temperature
shutdown, the chip is latched off after the fourth occurance
and the I2C bit is latched HIGH and the FLT bar LOW. This
OTF counter and the FLT bar can be reset and the chip
restarted by either a power down/up and reload the I2C or
power can be left on and the reset accomplished by toggling
the I2C bit EN low then back HIGH.
External Output Voltage Selection
The output voltage can be selected by the I2C bus.
Additionally, the package offers two pins (SELVTOP1,
SELVTOP2) for independent 13V thru 19V output voltage
selection.
VSPEN1/2
0
0
0
0
1
1
1
1
VTOP1/2
x
x
0
1
0
0
1
1
TABLE 1.
VOUT1/2
VBOT1/2 SELVTOP1/2
(V)
0 0 13.3
1 0 14.3
x 1 18.3
x 1 19.3
0 x 13.3
1 x 14.3
0 x 18.3
1 x 19.3
I2C Bus Interface for ISL6422B
(Refer to Philips I2C Specification, Rev. 2.1)
Data transmission from main microprocessor to the ISL6422B
(and vice versa) takes place through the two wire I2C bus
interface, consisting of the two lines, SDA and SCL. Both SDA
and SCL are bidirectional lines. They are connected to a
positive supply voltage via a pull-up resistor. (Pull-up resistors
to positive supply voltage must be externally connected). When
the bus is free, both lines are HIGH. The output stages of
ISL6422B will have an open drain/open collector in order to
perform the wired-AND function. Data on the I2C bus can be
transferred up to 100kbps in the standard-mode or up to
400kbps in the fast-mode. The level of logic “0” and logic “1”
depends value of VDD as per the “Electrical Specifications”
table on page 5. One clock pulse is generated for each data bit
transferred.
Data Validity
The data on the SDA line must be stable during the HIGH
period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is
LOW. Refer to Figure 4.
SDA
SCL
DATA LINE CHANGE
STABLE OF DATA
DATA VALID ALLOWED
FIGURE 4. DATA VALIDITY
START and STOP Conditions
As shown in Figure 5, START condition is a HIGH to LOW
transition of the SDA line while SCL is HIGH.
11 FN6486.2
September 8, 2015
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet ISL6422B.PDF ] | |
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