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ISL54105A の電気的特性と機能

ISL54105AのメーカーはIntersilです、この部品の機能は「TMDS Regenerators」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL54105A
部品説明 TMDS Regenerators
メーカ Intersil
ロゴ Intersil ロゴ 




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ISL54105A Datasheet, ISL54105A PDF,ピン配置, 機能
® Key Features
Data Sheet
June 4, 2008
ISL54105A
FN6716.0
TMDS Regenerator
The ISL54105A is a high-performance TMDS timing
regenerator containing a programmable equalizer and a
clock data recovery (CDR) function for each of the 3 TMDS
pairs in an HDMI or DVI signal. The TMDS data outputs of
the ISL54105A are regenerated and perfectly aligned to the
regenerated TMDS clock signal, creating an extremely
clean, low-jitter DVI/HDMI signal that can be easily
decoded by any TMDS receiver.
The ISL54105A can be used as a cable extender, to clean
up a noisy/jittery TMDS source, or to provide a very stable
TMDS signal to a finicky DVI or HDMI receiver.
Block Diagram
2
RXC
TERMINATION
Features
• Clock Data Recovery and Retiming
• Programmable pre-emphasis on output driver
• Programmable internal 50Ω, 100Ω, or high-Z termination
• Stand-alone or I2C software-controlled operation
• 72 lead, 10mm x 10mm QFN package
• Pb-free (RoHS compliant)
Applications
• DVI/HDMI extenders
• Televisions/PC monitors/projectors
PLL 2 TXC
2
RX0
2
RX1
2
RX2
CH0
TERMINATION AND
EQUALIZATION
CH1
CH2
RES_TERM
RES_BIAS
BIAS GENERATION
CDR D
CK
D
CDR
CK
D
CDR
CK
FIFO
2 TX0
2
TX1
2
TX2
SDA
SCL
ADDR
7
PD
RESET
CONFIGURATION AND CONTROL
ACTIVITY
DETECT
Ordering Information
PART NUMBER
TEMP. RANGE (°C)
PACKAGE
PKG. DWG. #
ISL54105ACRZ
0 to +70
72 Ld QFN (Pb-Free)
L72.10x10B
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 Page





ISL54105A pdf, ピン配列
ISL54105A
Electrical Specifications Specifications apply for VD = 3.3V, pixel rate = 165MHz, TA = +25°C, RES_TERM = 1kΩ, RES_BIAS = 3.16kΩ,
TMDS output load = 50Ω, TMDS output termination voltage VTERM = 3.3V unless otherwise noted.
SYMBOL
PARAMETER
COMMENT
MIN
(Note 2)
TYP
MAX
(Note 2)
UNIT
DIGITAL OUTPUT CHARACTERISTICS
VOH
Output HIGH Voltage, IO = 8mA
VOL Output LOW Voltage, IO = -8mA
POWER SUPPLY REQUIREMENTS
2.4 V
0.4 V
VD Supply Voltage
ID Supply Current
Inputs driven by 165Mpixel/s
TMDS signals.
Default register settings
3 3.3 3.6 V
357 405
mA
ID Supply Current in Power-down Mode
All available inputs driven by
165Mpixel/s TMDS signals.
20 26 mA
AC TIMING CHARACTERISTICS (2-WIRE INTERFACE)
fSCL
tAA
tBUF
SCL Clock Frequency
SCL LOW to SDA Data Out Valid
Time the Bus Must be Free Before a New
Transmission Can Start
0 400 kHz
200 470
ns
1.3 µs
tLOW
Clock LOW Time
1.3 0.1
µs
tHIGH Clock HIGH Time
0.6 0.2
µs
tSU:STA Start Condition Setup Time
0.6 0.03
µs
tHD:STA Start Condition Hold Time
0.6 0.07
µs
tSU:DAT Data In Setup Time
100 0.03
ns
tHD:DAT Data In Hold Time
0 ns
tSU:STO Stop Condition Setup Time
0.6 µs
tDH Data Output Hold Time
160 ns
NOTE:
2. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
3. Operation up to 165MHz is guaranteed. While many parts will typically operate up to 225MHz, operation above 165MHz is not guaranteed.
SCL
tSU:STA
SDA IN
SDA OUT
tF tHIGH
tSU:DAT
tHD:STA
tLOW
tR
tHD:DAT
tAA tDH
FIGURE 1. 2-WIRE INTERFACE TIMING
tSU:STO
tBUF
3 FN6716.0
June 4, 2008


3Pages


ISL54105A 電子部品, 半導体
ISL54105A
Register Listing
ADDRESS REGISTER (DEFAULT VALUE)
0x00
Device ID (read only)
0x01
Channel Activity Detect (read only)
0x02
Channel Selection (0x0C)
0x03
Input Control (0x12)
Recommended default: 0x63
BIT(S) FUNCTION NAME
DESCRIPTION
3:0 Device Revision
1 = initial silicon, 2 = second revision, etc.
7:4 Device ID
3 = ISL54105A
1:0 Reserved
Reserved
2 Activity Detect
0: TMDS clock not present on RXC
1: TMDS clock detected on RXC
3:0 Reserved
This nibble should always be set to 0xC.
4 Reset
Full chip reset. Write a 1 to reset. Will set itself to 0 when
reset is complete.
5 Power-down
0: Normal Operation
1: Puts the chip in a minimal power consumption mode,
turning off all TMDS outputs and open-circuiting all TMDS
inputs.
This bit is OR'ed with the Power-down input pin. If either is
set, the chip will enter power-down. Serial
I/O stays operational in PD mode.
Note: When exiting Power-down, a termination resistor
Recalibration cycle must be run to re-trim the termination
resistors (see register 0x03[7]).
0 Reserved
Set to 1. Default value of 0 is OK, set to 1 to slightly reduce
power consumption.
1 Reserved
Set to 1.
2 Tri-state Clock
Inputs
0: Clock inputs are terminated into 50Ω/100Ω.
1: Clock inputs are tri-stated (to allow chip to operate in
parallel with another TMDS receiver with fixed 50Ω
termination)
3 Tri-state Data Inputs 0: Data inputs are terminated into 50Ω/100Ω.
1: Data inputs are tri-stated (to allow chip to operate in
parallel with another TMDS receiver with fixed 50Ω
termination)
4 Activity Detect Mode 0: AC Activity. Activity detection is based on the presence of
AC activity on TMDS clock inputs. This setting (along with a
hysteresis of 20mV enabled) provides reliable activity
detection. (recommended setting)
1: Common Mode Voltage. If the common mode voltage is
above ~3.05V, the input is considered in active. This method
has been found to be unreliable with small signal swings and
should not be used. This setting is the silicon default but
should be changed in software for more reliable activity
detection.
5 Clock Rx Hysteresis Enables hysteresis for the clock inputs to prevent false clock
detection when both inputs are high. Data inputs do not get
hysteresis.
0: TMDS input hysteresis disabled
1: TMDS input hysteresis enabled. Eliminates false activity
detects on unconnected channels. (recommended setting)
6 Clock Rx Hysteresis Controls the amount of hysteresis in the clock inputs.
Magnitude
0: 10mV
1: 20mV (recommended setting)
7 Recalibrate
0: Normal Operation
1: Recalibrates termination resistance. To recalibrate, take
this bit high, wait at least 1ms, then take this bit low.
Calibration is automatically done after power-on, but
performing a recalibration after the supply voltage and
temperature have stabilized may result in termination
resistances closer to the desired 50Ω.
6 FN6716.0
June 4, 2008

6 Page



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部品番号部品説明メーカ
ISL54105

TMDS Regenerator

Intersil
Intersil
ISL54105A

TMDS Regenerators

Intersil
Intersil


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