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PDF K4B4G1646Q Data sheet ( Hoja de datos )
| Número de pieza | K4B4G1646Q | |
| Descripción | 4Gb Q-die DDR3L SDRAM | |
| Fabricantes | Samsung | |
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Rev. 0.5, Apr. 2013
K4B4G1646Q
Preliminary
4Gb Q-die DDR3L SDRAM Olny x16 1.35V
96FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
CAUTION :
This document includes some items still under discussion in JEDEC
Therefore, those may be changed without pre-notice based on JEDEC progress.
In addition, it is highly recommended that you not send specs without Samsung’s permission.
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
2013 Samsung Electronics Co., Ltd. All rights reserved.
-1-
1 page  
K4B4G1646Q
datasheet
1. Ordering Information
[ Table 1 ] Samsung 4Gb DDR3L Q-die ordering information table
Organization
DDR3L-1066 (7-7-7)
DDR3L-1333 (9-9-9)3
256Mx16
K4B4G1646Q-HYF8
NOTE :
1. Speed bin is in order of CL-tRCD-tRP.
2. Backward compatible to DDR3L-1333(9-9-9), DDR3L-1066(7-7-7)
3. Backward compatible to DDR3L-1066(7-7-7)
K4B4G1646Q-HYH9
Preliminary Rev. 0.5
DDR3L SDRAM
DDR3L-1600 (11-11-11)2
K4B4G1646Q-HYK0
Package
96 FBGA
2. Key Features
[ Table 2 ] 4Gb DDR3 Q-die Speed bins
Speed
DDR3-800
6-6-6
tCK(min)
2.5
CAS Latency
6
tRCD(min)
15
tRP(min)
15
tRAS(min)
37.5
tRC(min)
52.5
DDR3-1066
7-7-7
1.875
7
13.125
13.125
37.5
50.625
DDR3-1333
9-9-9
1.5
9
13.5
13.5
36
49.5
DDR3-1600
11-11-11
1.25
11
13.75
13.75
35
48.75
Unit
ns
nCK
ns
ns
ns
ns
• JEDEC standard 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
• VDDQ = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
• 400 MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin,
667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin
• 8 Banks
• Programmable CAS Latency(posted CAS): 5,6,7,8,9,10,11
• Programmable Additive Latency: 0, CL-2 or CL-1 clock
• Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6
(DDR3-1066), 7 (DDR3-1333) and 8 (DDR3-1600)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting
address “000” only), 4 with tCCD = 4 which does not allow seamless
read or write [either On the fly using A12 or MRS]
• Bi-directional Differential Data-Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin
(RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than TCASE 85C, 3.9us at
85C < TCASE < 95 C
• Asynchronous Reset
• Package : 96 balls FBGA - x16
• All of Lead-Free products are compliant for RoHS
• All of products are Halogen-free
The 4Gb DDR3 SDRAM Q-die is organized as a 32Mbit x 16 I/Os x 8banks,
device. This synchronous device achieves high speed double-data-rate
transfer rates of up to 1600Mb/sec/pin (DDR3-1600) for general applica-
tions.
The chip is designed to comply with the following key DDR3 SDRAM fea-
tures such as posted CAS, Programmable CWL, Internal (Self) Calibration,
On Die Termination using ODT pin and Asynchronous Reset .
All of the control and address inputs are synchronized with a pair of exter-
nally supplied differential clocks. Inputs are latched at the crosspoint of dif-
ferential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-
ion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. The DDR3 device operates
with a single 1.35V(1.28V~1.45V) or 1.5V(1.425V~1.575V) power supply
and 1.35V(1.28V~1.45V) or 1.5V(1.425V~1.575V).
The 4Gb DDR3 Q-die device is available in 96ball FBGAs(x16).
NOTE : 1. This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device Operation & Timing
Diagram”.
2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
-5-
5 Page 
K4B4G1646Q
datasheet
Preliminary Rev. 0.5
DDR3L SDRAM
8. AC & DC Input Measurement Levels
8.1 AC & DC Logic input levels for single-ended signals
[ Table 7 ] Single-ended AC & DC input levels for Command and Address(1.35V)
Symbol
Parameter
DDR3L-800/1066/1333/1600
Min.
Max.
Unit NOTE
1.35V
VIH.CA(DC90)
DC input logic high
VREF + 90
VDD
mV 1
VIL.CA(DC90)
DC input logic low
VSS
VREF - 90
mV 1
VIH.CA(AC160)
AC input logic high
VREF + 160
Note 2
mV 1,2,5
VIL.CA(AC160)
AC input logic low
Note 2
VREF - 160
mV 1,2,5
VIH.CA(AC135)
AC input logic high
VREF+135
Note 2
mV 1,2,5
VIL.CA(AC135)
AC input logic lowM
Note 2
VREF-135
mV 1,2,5
VREFCA(DC)
Reference Voltage for ADD, CMD inputs
0.49*VDD
0.51*VDD
V 3,4
NOTE :
1. For input only pins except RESET, VREF = VREFCA(DC)
2. See "Overshoot and Undershoot specifications" section.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 13.5 mV).
4. For reference: approx. VDD/2 +/- 13.5 mV
5. These levels apply for 1.35 Volt operation only. If the device is operated at 1.5 V , the respective levels in JESD79-3 (VIH/L.CA(DC100), VIH/L.CA(AC175), VIHL.CA(AC150),
VIH/L.CA(AC135), VIH/L.CA(AC125)etc.) apply. The 1.5 V levels (VIH/L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), VIH/L.CA(AC135), VIHL.CA(AC125)etc.) do not
apply when the device is operated in the 1.35 voltage range.
[ Table 8 ] Single-ended AC & DC input levels for Command and Address(1.5V)
Symbol
Parameter
DDR3-800/1066/1333/1600
Min.
Max.
Unit NOTE
1.5V
VIH.CA(DC100)
VIL.CA(DC100)
VIH.CA(AC175)
VIL.CA(AC175)
VIH.CA(AC150)
VIL.CA(AC150)
VREFCA(DC)
DC input logic high
DC input logic low
AC input logic high
AC input logic low
AC input logic high
AC input logic low
Reference Voltage for ADD, CMD inputs
VREF + 100
VSS
VREF + 175
Note 2
VREF+150
Note 2
0.49*VDD
VDD
VREF - 100
Note 2
VREF - 175
Note 2
VREF-150
0.51*VDD
mV 1,5
mV 1,6
mV 1,2,7
mV 1,2,8
mV 1,2,7
mV 1,2,8
V 3,4,9
NOTE :
1. For input only pins except RESET, VREF = VREFCA(DC)
2. See "Overshoot and Undershoot specifications" section.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefCA(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
5. VIH(dc) is used as a simplified symbol for VIH.CA(DC100)
6. VIL(dc) is used as a simplified symbol for VIL.CA(DC100)
7. VIH(ac) is used as a simplified symbol for VIH.CA(AC175), VIH.CA(AC150), VIH.CA(AC135), and VIH.CA(AC125); VIH.CA(AC175) value is used when Vref + 0.175V is
referenced, VIH.CA(AC150) value is used when Vref + 0.150V is referenced, VIH.CA(AC135) value is used when Vref + 0.135V is referenced, and VIH.CA(AC125) value is
used when Vref + 0.125V is referenced.
8. VIL(ac) is used as a simplified symbol for VIL.CA(AC175), VIL.CA(AC150), VIL.CA(AC135) and VIL.CA(AC125); VIL.CA(AC175) value is used when Vref - 0.175V is
referenced, VIL.CA(AC150) value is used when Vref - 0.150V is referenced, VIL.CA(AC135) value is used when Vref - 0.135V is referenced, and VIL.CA(AC125) value is
used when Vref - 0.125V is referenced.
9. VrefCA(DC) is measured relative to VDD at the same point in time on the same device
- 11 -
11 Page | ||
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