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PDF ADP5080 Data sheet ( Hoja de datos )
| Número de pieza | ADP5080 | |
| Descripción | High Efficiency Integrated Power Solution | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
High Efficiency Integrated Power Solution
for Multicell Lithium Ion Applications
ADP5080
FEATURES
Wide input voltage range: 4.0 V to 15 V
High efficiency architecture
Up to 2 MHz switching frequency
6 synchronous rectification dc-to-dc converters
Channel 1 buck regulator: 3 A maximum
Channel 2 buck regulator: 1.15 A maximum
Channel 3 buck regulator: 1.5 A maximum
Channel 4 buck regulator: 0.8 A maximum
Channel 5 buck regulator: 2 A maximum
Channel 6 configurable buck or buck boost regulator
2 A maximum for buck regulator configuration
1.5 A maximum for buck boost regulator configuration
Channel 7 high voltage, high performance LDO regulator:
30 mA maximum
2 low quiescent current keep-alive LDO regulators
LDO1 regulator: 400 mA maximum
LDO2 regulator: 300 mA maximum
Control circuit
Charge pump for internal switching driver power supply
I2C-programmable output levels and power sequencing
Package: 72-ball, 4.5 mm × 4.0 mm × 0.6 mm WLCSP
(0.5 mm pitch)
APPLICATIONS
DSLR cameras
Non-reflex (mirrorless) cameras
Portable instrumentation
GENERAL DESCRIPTION
The ADP5080 is a fully integrated, high efficiency power
solution for multicell lithium ion battery applications. The
device can connect directly to the battery, which eliminates
the need for preregulators and, therefore, increases the battery
life of the system.
The ADP5080 integrates two keep-alive LDO regulators, five
synchronous buck regulators, a configurable four-switch buck
boost regulator, and a high voltage LDO regulator. The ADP5080
is a highly integrated power solution that incorporates all power
MOSFETs, feedback loop compensation, voltage setting resistor
dividers, and discharge switches, as well as a charge pump to
generate a global bootstrap voltage.
FUNCTIONAL BLOCK DIAGRAM
SCL
SDA
ENABLE
FAULT
4V TO 15V
4V TO 15V
4V TO 15V
4V TO 15V
4V TO 15V
4V TO 15V
4V TO 15V
5V TO 25V
I2C
INTERFACE
CONTROL
LOGIC
LDO1
CH1 BUCK
REGULATOR
CH 3 BUCK
REGULATOR
CH 5 BUCK
REGULATOR
CH7 LDO
REGULATOR
OSCILLATOR
VOLTAGE
REFERENCE
CHARGE
PUMP
LDO2
CH2 BUCK
REGULATOR
CH 4 BUCK
REGULATOR
CH 6
BUCK BOOST
REGULATOR
5.0V TO 5.5V, 400mA
3V TO 3.3V, 300mA
0.80V TO 1.20V, 3A
1.0V TO 3.3V, 1.15A
1.2V TO 1.8V/ADJ, 1.5A
1.8V TO 3.55V/ADJ, 0.8A
3.0V TO 5.0V, 2A
3.5V TO 5.5V/ADJ
BUCK ONLY: 2A
BUCK BOOST: 1.5A
5V TO 12V, 30mA
Figure 1.
All these features help to minimize the number of external
components and PCB space required, providing significant
advantages for portable applications. The switching frequency
is selectable on each channel from 750 kHz to 2 MHz.
Key functions for power applications, such as soft start, selectable
preset output voltage, and flexible power-up and power-down
sequences, are provided on chip and are programmable via the
I2C interface with fused factory defaults. The ADP5080 is available
in a 72-ball WLCSP 0.5 mm pitch package.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
DC-TO-DC CONVERTER BLOCK SPECIFICATIONS
TJ = 25°C, VVBATT = 7.2 V, VVREG1 = VVDRx = 5 V, VVREG2 = VVDDIO = 3.3 V, unless otherwise noted.
Table 3.
Parameter
Symbol
Min
Typ
Max Unit
CHANNEL 1 SYNC BUCK REGULATOR
Channel 1 Output Voltage (FB1 Pin)
Fixed Voltage Range, 5 Bits VFB1 0.89
1.20 V
0.80 1.11 V
Feedback Voltage Accuracy
at Default VID Code
VFB1 (DEFAULT)
−0.8
+0.8 %
−1.3 +1.3 %
Load Regulation
∆VFB1/ILOAD1
0.15
%/A
Line Regulation
SW1A Pin
High-Side Power FET On Resistance
Low-Side Power FET On Resistance
SW1B Pin
High-Side Power FET On Resistance
Low-Side Power FET On Resistance
SW1A and SW1B Pins
Switch Current Limit
Minimum Off Time
Minimum Duty Cycle
Soft Start Time
COUT Discharge Switch On Resistance
CHANNEL 2 SYNC BUCK REGULATOR
Channel 2 Output Voltage (FB2 Pin)
Fixed Voltage Range, 4 Bits
Feedback Voltage Accuracy
at Default VID Code
∆VFB1/VPVIN1
RDSON_1AH
RDSON_1AL
RDSON_1BH
RDSON_1BL
ICL1
tOFF1 (MIN)
DMIN1
tSS1
RDIS1
VFB2
VFB2 (DEFAULT)
Load Regulation
∆VFB2/ILOAD2
3.1
1.0
−0.8
−1.3
0.004
250
130
175
95
4.0
115
0
4
125
3.3
+0.8
+1.3
0.25
%/V
mΩ
mΩ
mΩ
mΩ
A
ns
%
ms
Ω
V
%
%
%/A
Line Regulation
SW2 Pins
High-Side Power FET On Resistance
Low-Side Power FET On Resistance
Switch Current Limit
Minimum Off Time
Minimum Duty Cycle
Soft Start Time
COUT Discharge Switch On Resistance
CHANNEL 3 SYNC BUCK REGULATOR
Channel 3 Output Voltage (FB3 Pin)
Fixed Voltage Range, 3 Bits
Minimum Adjustable Voltage
Feedback Voltage Accuracy
at Default VID Code
∆VFB2/VPVIN2
RDSON_2H
RDSON_2L
ICL2
tOFF2 (MIN)
DMIN2
tSS2
RDIS2
VFB3
VFB3 (DEFAULT)
Load Regulation
∆VFB3/ILOAD3
1.2
1.2
−0.8
−1.3
0.004
235
165
1.8
100
0
4
125
1.8
0.8
+0.8
+1.3
0.17
%/V
mΩ
mΩ
A
ns
%
ms
Ω
V
V
%
%
%/A
Line Regulation
∆VFB3/VPVIN3
0.003
%/V
Rev. A | Page 5 of 64
ADP5080
Test Conditions/Comments
REDUCE_VOUT1 = 0
REDUCE_VOUT1 = 1
−25°C ≤ TJ ≤ +85°C
ILOAD1 = 20 mA to 2 A,
AUTO-PSM1 = 0
VPVIN1 = 5 V to 15 V, ILOAD = 1 A
ID = 100 mA
ID = 100 mA
ID = 100 mA, GATE_SCAL1 = 0
ID = 100 mA
Valley current, −25°C ≤ TJ ≤ +85°C
SS1 = 10
VFB1 = 1 V
−25°C ≤ TJ ≤ +85°C
ILOAD2 = 10 mA to 1.0 A,
AUTO-PSM2 = 0
VPVIN2 = 5 V to 15 V, ILOAD2 = 500 mA
ID = 100 mA
ID = 100 mA
Valley current, −25°C ≤ TJ ≤ +85°C
SS2 = 10
VFB2 = 1 V
VID3 = 111
−25°C ≤ TJ ≤ +85°C
ILOAD3 = 15 mA to 1.5 A,
AUTO-PSM3 = 0
VPVIN3 = 5 V to 15 V, ILOAD3 = 700 mA
5 Page 
Data Sheet
ADP5080
Pin No.
9C
1D
2D
3D
4D
5D
6D
7D
8D
9D
1E
2E
3E
4E
5E
6E
7E
Mnemonic
PVIN4
SW6A
SW6A
VDR6
FB6
GND
SYNC
FB5
FB4
SW4
PVIN6
PVIN6
BST16
SDA
SCL
GND
CLKO
8E VDR34
9E PGND4
1F PVIN1
2F PVIN1
3F FB1
4F EN
5F VDDIO
6F FREQ
7F FB3
8F PGND3
9F PGND3
1G SW1A
2G SW1B
3G VDR12
4G FB2
5G GND
6G FAULT
7G GND
8G SW3
9G SW3
1H PGND1
2H PGND1
3H PGND2
4H SW2
5H SW2
6H PVIN2
7H BST23
8H PVIN3
9H PVIN3
Description
Input Power Supply for Channel 4.
Primary Side Switching Node for Channel 6.
Primary Side Switching Node for Channel 6.
Low-Side FET Driver Power Supply for Channel 6. Connect this pin to VREG1.
Feedback Node for Channel 6.
Ground. All GND pins must be connected.
External Clock Input (CMOS Input Port). If this pin is not used, connect it to GND.
Feedback Node for Channel 5.
Feedback Node for Channel 4.
Switching Node for Channel 4.
Input Power Supply for Channel 6.
Input Power Supply for Channel 6.
High-Side FET Driver Power Supply for Channel 1 and Channel 6.
Data Input/Output for I2C Interface. Open-drain I/O port.
Clock Input for I2C Interface. For start-up requirements, see the I2C Interface section.
Ground. All GND pins must be connected.
Clock Output (CMOS Output Port). CLKO replicates the Channel 1 switching clock. This output is not available
when the SYNC pin is driven by an external clock. If this pin is not used, leave it open.
Low-Side FET Driver Power Supply for Channel 3 and Channel 4. Connect this pin to VREG1.
Power Ground for Channel 4.
Input Power Supply for Channel 1.
Input Power Supply for Channel 1.
Feedback Node for Channel 1.
Enable Control Input.
Supply Voltage for I2C Interface. Typically, this pin is connected externally to VREG2 or to the host I/O voltage.
Frequency Pin for the Internal Oscillator. To select the internal clock source oscillator, connect an external
100 kΩ resistor from the FREQ pin to GND.
Feedback Node for Channel 3.
Power Ground for Channel 3.
Power Ground for Channel 3.
Switching Node for Channel 1.
Switching Node for Channel 1.
Low-Side FET Driver Power Supply for Channel 1 and Channel 2. Connect this pin to VREG1.
Feedback Node for Channel 2.
Ground. All GND pins must be connected.
Fault Status Output Pin. This open-drain output port goes low when a fault occurs. Leave open if not used.
Ground. All GND pins must be connected.
Switching Node for Channel 3.
Switching Node for Channel 3.
Power Ground for Channel 1.
Power Ground for Channel 1.
Power Ground for Channel 2.
Switching Node for Channel 2.
Switching Node for Channel 2.
Input Power Supply for Channel 2.
High-Side FET Driver Power Supply for Channel 2 and Channel 3.
Input Power Supply for Channel 3.
Input Power Supply for Channel 3.
Rev. A | Page 11 of 64
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADP5080.PDF ] | |
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