HK24C64 Datasheet PDF - Hang Shun chip technology
| Part Number | HK24C64 | |
| Description | Two-Wire Serial EEPROM | |
| Manufacturers | Hang Shun chip technology | |
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Two-Wire Serial EEPROM
32K, 64K (8-bit wide)
FEATURES
Low voltage and low power operations:
HK24C32/HK24C64:
VCC = 1.8V to 5.5V
Maximum Standby current < 1µA (typically 0.02µA and 0.06µA @ 1.8V and 5.5V respectively).
32 bytes page write mode.
Partial page write operation allowed.
Internally organized: 4,096 × 8 (32K), 8,192 × 8 (64K).
Standard 2-wire bi-directional serial interface.
Schmitt trigger, filtered inputs for noise protection.
Self-timed Write Cycle (5ms maximum).
800 kHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility.
Automatic erase before write operation.
Write protect pin for hardware data protection.
High reliability: typically 1, 000,000 cycles endurance.
100 years data retention.
Industrial temperature range (-40℃ to 85℃).
Standard 8-lead DIP/SOP/ MSOP/TSSOP/DFN and 5-lead SOT23/TSOT23 Pb-free packages.
DESCRIPTION
The HK24C32/24C64 series are 32,768/65,536 bits of serial Electrical Erasable and Programmable Read
Only Memory, commonly known as EEPROM. They are organized as 4096/8192 words of 8 bits (one byte)
each. The devices are fabricated with proprietary advanced CMOS process for low power and low voltage
applications. These devices are available in standard 8-lead DIP, 8-lead SOP, 8-lead MSOP, 8-lead
TSSOP, 8-lead DFN, 5-lead SOT23, and 5-lead TSOT23 packages. A standard 2-wire serial interface is
used to address all read and write functions. Our extended VCC range (1.8V to 5.5V) devices enables wide
spectrum of applications.
PIN CONFIGURATION
Pin Name
A2, A1, A0
SDA
SCL
WP
NC
Pin Function
Device Address Inputs
Serial Data Input / Open Drain Output
Serial Clock Input
Write Protect
No-Connect
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WRITE OPERATIONS
(A) BYTE WRITE
A write operation requires two 8-bit data word address following the device address word and
ACKNOWLEDGE signal. Upon receipt of this address, the EEPROM will respond with a “0” and then
clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will again output
a “0”. The addressing device, such as a microcontroller, must terminate the write sequence with a
STOP condition. At this time the EEPROM enters into an internally-timed write cycle state. All inputs
are disabled during this write cycle and the EEPROM will not respond until the writing is completed
(figure 3).
(B) PAGE WRITE
The 32K/64K EEPROM are capable of 32-byte page write.
A page write is initiated the same way as a byte write, but the microcontroller does not send a STOP
condition after the first data word is clocked in. The microcontroller can transmit up to 31 more data
words after the EEPROM acknowledges receipt of the first data word. The EEPROM will respond with a
“0” after each data word is received. The microcontroller must terminate the page write sequence with a
STOP condition (see Figure 4).
The lower five bits of the data word address are internally incremented following the receipt of each data
word. The higher data word address bits are not incremented, retaining the memory page row location.
If more than 32 data words are transmitted to the EEPROM, the data word address will “roll over” and
the previous data will be overwritten.
(C) ACKNOWLEDGE POLLING
ACKNOWLEDGE polling may be used to poll the programming status during a self-timed internal
programming. By issuing a valid read or write address command, the EEPROM will not acknowledge at
the 9th clock cycle if the device is still in the self-timed programming mode. However, if the programming
completes and the chip has returned to the STANDBY mode, the device will return a valid
ACKNOWLEDGE signal at the 9th clock cycle.
READ OPERATIONS
The read command is similar to the write command except the 8th read/write bit in address word is set to “1”.
The three read operation modes are described as follows:
(A) CURRENT ADDRESS READ
The EEPROM internal address word counter maintains the last read or write address plus one if the
power supply to the device has not been cut off. To initiate a current address read operation, the micro-
controller issues a START bit and a valid device address word with the read/write bit (8th) set to “1”. The
EEPROM will response with an ACKNOWLEDGE signal on the 9th serial clock cycle. An 8-bit data word
will then be serially clocked out. The internal address word counter will then automatically increase by
one. For current address read the micro-controller will not issue an ACKNOWLEDGE signal on the 18th
clock cycle. The micro-controller issues a valid STOP bit after the 18th clock cycle to terminate the read
operation. The device then returns to STANDBY mode (see Figure 5).
(B) SEQUENTIAL READ
The sequential read is very similar to current address read. The micro-controller issues a START bit
and a valid device address word with read/write bit (8th) set to “1”. The EEPROM will response with an
ACKNOWLEDGE signal on the 9th serial clock cycle. An 8-bit data word will then be serially clocked out.
Meanwhile the internally address word counter will then automatically increase by one.
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for HK24C64 electronic component. |
| Information | Total 17 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ HK24C64.PDF Datasheet ] | |
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