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HK24C32 の電気的特性と機能

HK24C32のメーカーはHang Shun chip technologyです、この部品の機能は「Two-Wire Serial EEPROM」です。


製品の詳細 ( Datasheet PDF )

部品番号 HK24C32
部品説明 Two-Wire Serial EEPROM
メーカ Hang Shun chip technology
ロゴ Hang Shun chip technology ロゴ 




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HK24C32 Datasheet, HK24C32 PDF,ピン配置, 機能
Two-Wire Serial EEPROM
32K, 64K (8-bit wide)
FEATURES
Low voltage and low power operations:
HK24C32/HK24C64:
VCC = 1.8V to 5.5V
Maximum Standby current < 1µA (typically 0.02µA and 0.06µA @ 1.8V and 5.5V respectively).
32 bytes page write mode.
Partial page write operation allowed.
Internally organized: 4,096 × 8 (32K), 8,192 × 8 (64K).
Standard 2-wire bi-directional serial interface.
Schmitt trigger, filtered inputs for noise protection.
Self-timed Write Cycle (5ms maximum).
800 kHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility.
Automatic erase before write operation.
Write protect pin for hardware data protection.
High reliability: typically 1, 000,000 cycles endurance.
100 years data retention.
Industrial temperature range (-40to 85).
Standard 8-lead DIP/SOP/ MSOP/TSSOP/DFN and 5-lead SOT23/TSOT23 Pb-free packages.
DESCRIPTION
The HK24C32/24C64 series are 32,768/65,536 bits of serial Electrical Erasable and Programmable Read
Only Memory, commonly known as EEPROM. They are organized as 4096/8192 words of 8 bits (one byte)
each. The devices are fabricated with proprietary advanced CMOS process for low power and low voltage
applications. These devices are available in standard 8-lead DIP, 8-lead SOP, 8-lead MSOP, 8-lead
TSSOP, 8-lead DFN, 5-lead SOT23, and 5-lead TSOT23 packages. A standard 2-wire serial interface is
used to address all read and write functions. Our extended VCC range (1.8V to 5.5V) devices enables wide
spectrum of applications.
PIN CONFIGURATION
Pin Name
A2, A1, A0
SDA
SCL
WP
NC
Pin Function
Device Address Inputs
Serial Data Input / Open Drain Output
Serial Clock Input
Write Protect
No-Connect

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HK24C32 pdf, ピン配列
PIN DESCRIPTIONS
(A) SERIAL CLOCK (SCL)
The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of this
clock is to clock data out of the EEPROM device.
(B) DEVICE / CHIP SELECT ADDRESSES (A2, A1, A0)
These are the chip select input signals for the serial EEPROM devices. Typically, these signals are
hardwired to either VIH or VIL. If left unconnected, they are internally recognized as VIL.
(C) SERIAL DATA LINE (SDA)
SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can be
wired-OR with other open-drain output devices.
(D) WRITE PROTECT (WP)
The HK24C32/24C64 devices have a WP pin to protect the whole EEPROM array from programming.
Programming operations are allowed if WP pin is left un-connected or input to VIL. Conversely all
programming functions are disabled if WP pin is connected to VIH or VCC. Read operations is not affected
by the WP pin’s input level.
MEMORY ORGANIZATION
The HK24C32/24C64 devices have 128/256 pages respectively. Since each page has 32 bytes, random
word addressing to HK24C32/24C64 will require 12/13 bitsdata word addresses respectively.
DEVICE OPERATION
(A) SERIAL CLOCK AND DATA TRANSITIONS
The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when
Serial clock SCL is at VIL. Any SDA signal transition may interpret as either a START or STOP condition
as described below.
(B) START CONDITION
With SCL  VIH, a SDA transition from high to low is interpreted as a START condition. All valid
commands must begin with a START condition.
(C) STOP CONDITION
With SCL  VIH, a SDA transition from low to high is interpreted as a STOP condition. All valid read or
write commands end with a STOP condition. The device goes into the STANDBY mode if it is after a
read command. A STOP condition after page or byte write command will trigger the chip into the
STANDBY mode after the self-timed internal programming finish (see Figure 1).
(D) ACKNOWLEDGE
The 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The EEPROM
acknowledges the data or address by outputting a "0" after receiving each word. The ACKNOWLEDGE
signal occurs on the 9th serial clock after each word.


3Pages


HK24C32 電子部品, 半導体
Unlike current address read, the micro-controller sends an ACKNOWLEDGE signal on the 18th clock
cycle signaling the EEPROM device that it wants another byte of data. Upon receiving the
ACKNOWLEDGE signal, the EEPROM will serially clocked out an 8-bit data word based on the
incremented internal address counter. If the micro-controller needs another data, it sends out an
ACKNOWLEDGE signal on the 27th clock cycle. Another 8-bit data word will then be serially clocked out.
This sequential read continues as long as the micro-controller sends an ACKNOWLEDGE signal after
receiving a new data word. When the internal address counter reaches its maximum valid address, it
rolls over to the beginning of the memory array address. Similar to current address read, the micro-
controller can terminate the sequential read by not acknowledging the last data word received, but
sending a STOP bit afterwards instead (figure 6).
(C) RANDOM READ
Random read is a two-steps process. The first step is to initialize the internal address counter with a
target read address using a “dummy write” instruction. The second step is a current address read.
To initialize the internal address counter with a target read address, the micro-controller issues a START
bit first, follows by a valid device address with the read/write bit (8th) set to “0”. The EEPROM will then
acknowledge. The micro-controller will then send two address words. Again the EEPROM will
acknowledge. Instead of sending a valid written data to the EEPROM, the micro-controller performs a
current address read instruction to read the data. Note that once a START bit is issued, the EEPROM
will reset the internal programming process and continue to execute the new instruction - which is to
read the current address (figure 7).
Figure 3: Byte Write
S
T
A
R DEVICE
T ADDRESS
SDA LINE
W
R
I
T FIRST WORD
E ADDRESS
***#
SECOND WORD
ADDRESS
M
LRA
M
A
S
S/C
S
C
B
B WK
B
K
LA
SC
BK
DATA
S
T
O
P
A
C
K
Figure 4: Page Write
S
T
A
R DEVICE
T ADDRESS
SDA LINE
W
R
I
T FIRST WORD
E ADDRESS(N)
***#
SECOND WORD
ADDRESS(N)
M
LRA
M
A
S
S/C
S
C
B
B WK
B
K
LA
SC
BK
DATA(N)
S
T
O
DATA(N+X) P
...
AA
CC
KK

6 Page



ページ 合計 : 17 ページ
 
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共有リンク

Link :


部品番号部品説明メーカ
HK24C32

Two-Wire Serial EEPROM

Hang Shun chip technology
Hang Shun chip technology


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