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PDF F59L2G81A Data sheet ( Hoja de datos )
| Número de pieza | F59L2G81A | |
| Descripción | 2 Gbit (256M x 8) 3.3V NAND Flash Memory | |
| Fabricantes | Elite Semiconductor | |
| Logotipo |  |
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ESMT
Flash
FEATURES
Voltage Supply: 3.3V (2.7V ~ 3.6V)
Organization
- Memory Cell Array: (256M + 16M) x 8bit
- Data Register: (2K + 64) x 8bit
Automatic Program and Erase
- Page Program: (2K + 64) byte
- Block Erase: (128K + 4K) byte
Page Read Operation
- Page Size: (2K + 64) bytes
- Random Read: 25us (Max.)
- Serial Access: 25ns (Min.)
Memory Cell: 1bit/Memory Cell
Fast Write Cycle Time
- Program time: 350us (Typ.)
- Block Erase time: 3.5ms (Typ.)
Command/Address/Data Multiplexed I/O Port
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
F59L2G81A
2 Gbit (256M x 8)
3.3V NAND Flash Memory
Reliable CMOS Floating Gate Technology
- ECC Requirement: 4bit/512Byte
- Endurance: 100K Program/Erase cycles
- Data Retention: 10 years
Command Register Operation
Automatic Page 0 Read at Power-Up Option
- Boot from NAND support
- Automatic Memory Download
NOP: 4 cycles
Cache Program Operation for High Performance Program
Cache Read Operation
Copy-Back Operation
- EDO mode
- OTP Operation
- Two-Plane Operation
Bad-Block-Protect
ORDERING INFORMATION
Product ID
Speed
Package
F59L2G81A -25TG
25 ns
48 pin TSOPI
F59L2G81A -25BG
25 ns
63 ball BGA
Comments
Pb-free
Pb-free
GENERAL DESCRIPTION
The device is a 256Mx8bit with spare 16Mx8bit capacity. The
device is offered in 3.3V VCC Power Supply. Its NAND cell
provides the most cost-effective solution for the solid state mass
storage market. The memory is divided into blocks that can be
erased independently so it is possible to preserve valid data
while old data is erased.
The device contains 2048 blocks, composed by 64 pages
consisting in two NAND structures of 32 series connected Flash
cells. A program operation allows to write the 2112-Word page in
typical 350us and an erase operation can be performed in typical
3.5ms on a 128K-Byte for X8 device block.
Data in the page mode can be read out at 25ns cycle time per
Word. The I/O pins serve as the ports for address and command
inputs as well as data input/output. The copy back function
allows the optimization of defective blocks management: when a
page program operation fails the data can be directly
programmed in another page inside the same array section
without the time consuming serial data insertion phase. The
cache program feature allows the data insertion in the cache
register while the data register is copied into the Flash array.
This pipelined program operation improves the program
throughput when long files are written inside the memory. A
cache read feature is also implemented. This feature allows to
dramatically improving the read throughput when consecutive
pages have to be streamed out. This device includes extra
feature: Automatic Read at Power Up.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.3
1/55
1 page  
ESMT
F59L2G81A
Product Introduction
The device is a 2,112Mbit memory organized as 128K rows (pages) by 2,112x8 columns. Spare 64x8 columns are located from
column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommodating data transfer between
the I/O buffers and memory during page read and page program operations. The program and read operations are executed on a page
basis, while the erase operation is executed on a block basis. The memory array consists of 2048 separately erasable 128K-byte
blocks. It indicates that the bit-by-bit erase operation is prohibited on the device.
The device has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future
densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing
WE to low while CE is low. Those are latched on the rising edge of WE . Command Latch Enable (CLE) and Address Latch
Enable (ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For
example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block
erase and page program, require two cycles: one cycle for setup and the other cycle for execution.
In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
page without need for transporting the data to and from the external buffer memory.
Command Set
Function
1st Cycle
2nd Cycle
Acceptable Command
during Busy
Read
00h 30h
Read for Copy Back
00h 35h
Read ID
Reset
90h -
FFh -
O
Page Program
80h 10h
Copy-Back Program
85h 10h
Block Erase
Random Data Input(1)
Random Data Output(1)
Read Status
Read Status 2
Two-Plane Read(3)
60h
85h
05h
70h
F1h
60h-60h
D0h
-
E0h
-
-
30h
O
O
Two-Plane Read for Copy-Back
Two-Plane Random Data Output (1)(3)
Two-Plane Page Program(2)
Two-Plane Copy-Back Program(2)
60h-60h
00h-05h
80h-11h
85h-11h
35h
E0h
81h-10h
81h-10h
Two-Plane Block Erase
60h-60h
D0h
Cache Program
80h 15h
Cache Read
31h -
Read Start For Last Page Cache Read
Two-Plane Cache Read(3)
Two-Plane Cache Program(2)
3Fh
60h-60h
80h-11h
-
33h
81h-15h
NOTE:
1. Random Data Input/Output can be executed in a page.
2. Any command between 11h and 80h/81h/85h is prohibited except 70h/F1h and FFh.
3. Two-Plane Random Data Output must be used after Two-Plane Read operation or Two-Plane Cache Read operation.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.3
5/55
5 Page 
ESMT
F59L2G81A
Check “FFh” at the 1st Byte column address in
the spare area of the 1st and 2nd page in the
block.
For (i=0; i<Num_of_LUs; i++)
{
For (j=0; j<Blocks_Per_LU; j++)
{
Defect_Block_Found=False;
Read_Page(lu=i, block=j, page=0);
If (Data[coloumn= First_Byte_of_Spare_Area]!=FFh) Defect_Block_Found=True;
Read_Page(lu=i, block=j, page=1);
If (Data[coloumn= First_Byte_of_Spare_Area]!=FFh) Defect_Block_Found=True;
If (Defect_Block_Found) Mark_Block_as_Defective(lu=i, block=j);
}
}
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.3
11/55
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet F59L2G81A.PDF ] | |
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