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F59L1G81MA の電気的特性と機能

F59L1G81MAのメーカーはElite Semiconductorです、この部品の機能は「1 Gbit (128M x 8) 3.3V NAND Flash Memory」です。


製品の詳細 ( Datasheet PDF )

部品番号 F59L1G81MA
部品説明 1 Gbit (128M x 8) 3.3V NAND Flash Memory
メーカ Elite Semiconductor
ロゴ Elite Semiconductor ロゴ 




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F59L1G81MA Datasheet, F59L1G81MA PDF,ピン配置, 機能
ESMT
Flash
FEATURES
z Voltage Supply: 3.3V (2.7V~3.6V)
z Organization
- Memory Cell Array: (128M + 4M) x 8bit
- Data Register: (2K + 64) x 8bit
z Automatic Program and Erase
- Page Program: (2K + 64) Byte
- Block Erase: (128K + 4K) Byte
z Page Read Operation
- Page Size: (2K + 64) Byte
- Random Read: 25us (Max.)
- Serial Access: 25ns (Min.) (3.3V)
z Memory Cell: 1bit/Memory Cell
z Fast Write Cycle Time
- Program time: 350us - typical
- Block Erase time: 3.5ms - typical
z Command/Address/Data Multiplexed I/O Port
z Hardware Data Protection
- Program/Erase Lockout During Power Transitions
F59L1G81MA (2Y)
Operation Temperature Condition -40°C~85°C
1 Gbit (128M x 8)
3.3V NAND Flash Memory
z Reliable CMOS Floating Gate Technology
- ECC Requirement: - 4bit/512Byte,
- Endurance: 100K Program/Erase cycles
- Data Retention: 10 years
z Command Register Operation
z Automatic Page 0 Read at Power-Up Option
- Boot from NAND support
- Automatic Memory Download
z NOP: 4 cycles
z Cache Program Operation for High Performance Program
z Cache Read Operation
z Copy-Back Operation
z EDO mode
z OTP Operation
z Bad-Block-Protect
ORDERING INFORMATION
Product ID
F59L1G81MA -25TIG2Y
F59L1G81MA -25BIG2Y
F59L1G81MA -25BCIG2Y
Speed
25 ns
25 ns
25 ns
Package
48 pin TSOPI
63 ball BGA
67 ball BGA
Comments
Pb-free
Pb-free
Pb-free
GENERAL DESCRIPTION
The device is a 128Mx8bit with spare 4Mx8bit capacity. The
device is offered in 3.3V Vcc Power Supply. Its NAND cell
provides the most cost-effective solution for the solid state mass
storage market. The memory is divided into blocks that can be
erased independently so it is possible to preserve valid data
while old data is erased.
The device contains 1024 blocks, composed by 64 pages
consisting in two NAND structures of 32 series connected Flash
cells. A program operation allows to write the 2,112-Byte page in
typical 350us and an erase operation can be performed in typical
3.5ms on a 128K-Byte for X8 device block.
Data in the page mode can be read out at 25ns cycle time per
Byte. The I/O pins serve as the ports for address and command
inputs as well as data input/output. The copy back function
allows the optimization of defective blocks management: when a
page program operation fails the data can be directly
programmed in another page inside the same array section
without the time consuming serial data insertion phase. The
cache program feature allows the data insertion in the cache
register while the data register is copied into the Flash array.
This pipelined program operation improves the program
throughput when long files are written inside the memory. A
cache read feature is also implemented. This feature allows to
dramatically improving the read throughput when consecutive
pages have to be streamed out. This device includes extra
feature: Automatic Read at Power Up.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2014
Revision: 1.1
1/44

1 Page





F59L1G81MA pdf, ピン配列
ESMT
F59L1G81MA (2Y)
Operation Temperature Condition -40°C~85°C
BALL CONFIGURATION (TOP VIEW)
(BGA 67 Ball, 6.5mmx8mmx1.0mm Body, 0.8mm Ball Pitch)
12345678
A NC NC
NC NC NC
B NC WP ALE VSS CE WE R / B NC
C NC NC RE CLE NC NC NC NC
D NC NC NC NC NC NC
E NC NC NC NC NC NC
F NC NC NC NC NC NC
G NC I/O0 NC NC NC VCC
H NC NC I/O1 NC VCC I/O5 I/O7 NC
J NC VSS I/O2 I/O3 I/O4 I/O6 VSS NC
K NC NC NC
NC NC NC
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2014
Revision: 1.1
3/44


3Pages


F59L1G81MA 電子部品, 半導体
ESMT
F59L1G81MA (2Y)
Operation Temperature Condition -40°C~85°C
Product Introduction
The device is a 1Gbit memory organized as 128K rows (pages) by 2,112x8 columns. Spare 64x8 columns are located from column
address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommodating data transfer between the I/O
buffers and memory during page read and page program operations. The program and read operations are executed on a page basis,
while the erase operation is executed on a block basis. The memory array consists of 1,024 separately erasable 128K-byte blocks. It
indicates that the bit-by-bit erase operation is prohibited on the device.
The device has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future
densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing
WE to low while CE is low. Those are latched on the rising edge of WE . Command Latch Enable (CLE) and Address Latch
Enable (ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For
example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block
erase and page program, require two cycles: one cycle for setup and the other cycle for execution.
In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
page without need for transporting the data to and from the external buffer memory.
Command Set
Function
Read
Read for Copy Back
Read ID
Reset
Page Program
Copy-Back Program
Block Erase
Random Data Input(1)
Random Data Output(1)
Read Status
Cache Program
Cache Read
Read Start For Last Page
Cache Read
1st Cycle
00h
00h
90h
FFh
80h
85h
60h
85h
05h
70h
80h
31h
3Fh
2nd Cycle
30h
35h
-
-
10h
10h
D0h
-
E0h
-
15h
-
-
Acceptable Command
during Busy
O
O
Note: Random Data Input / Output can be executed in a page.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2014
Revision: 1.1
6/44

6 Page



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部品番号部品説明メーカ
F59L1G81MA

1 Gbit (128M x 8) 3.3V NAND Flash Memory

Elite Semiconductor
Elite Semiconductor


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