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F59D4G81A の電気的特性と機能

F59D4G81AのメーカーはElite Semiconductorです、この部品の機能は「4 Gbit (512M x 8 / 256M x 16) 1.8V NAND Flash Memory」です。


製品の詳細 ( Datasheet PDF )

部品番号 F59D4G81A
部品説明 4 Gbit (512M x 8 / 256M x 16) 1.8V NAND Flash Memory
メーカ Elite Semiconductor
ロゴ Elite Semiconductor ロゴ 




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F59D4G81A Datasheet, F59D4G81A PDF,ピン配置, 機能
ESMT
Flash
FEATURES
Voltage Supply: 1.8V (1.7V ~ 1.95V)
Organization
x8:
- Memory Cell Array: (512M + 8M) x 8bit
- Data Register: (2K + 64) x 8bit
x16:
- Memory Cell Array: (256M + 4M) x 16bit
- Data Register: (1K + 32) x 16bit
Automatic Program and Erase
x8:
- Page Program: (2K + 64) Byte
- Block Erase: (128K + 4K) Byte
x16:
- Page Program: (1K + 32) Word
- Block Erase: (64K + 2K) Word
Page Read Operation
- Page Size: (2K + 64) Byte (x8)
Page Size: (1K + 32) Word (x16)
- Random Read: 25us (Max.)
- Serial Access: 45ns (Min.)
Memory Cell: 1bit/Memory Cell
Fast Write Cycle Time
- Program time: 350us (Typ.)
- Block Erase time: 3.5ms (Typ.)
F59D4G81A / F59D4G161A
4 Gbit (512M x 8 / 256M x 16)
1.8V NAND Flash Memory
Command/Address/Data Multiplexed I/O Port
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
Reliable CMOS Floating Gate Technology
- ECC Requirement: x8 - 4bit/512Byte
x16 - 4bit/256Word
- Endurance: 100K Program/Erase cycles
- Data Retention: 10 years
Command Register Operation
Automatic Page 0 Read at Power-Up Option
- Boot from NAND support
- Automatic Memory Download
NOP: 4 cycles
Cache Program/Read Operation
Copy-Back Operation
Two-Plane Operation
EDO mode
Bad-Block-Protect
ORDERING INFORMATION
Product ID
Speed
Package
x8:
F59D4G81A -45TG
45 ns
48 pin TSOPI
x16:
F59D4G161A -45TG 45 ns
48 pin TSOPI
Comments
Pb-free
Pb-free
GENERAL DESCRIPTION
The device is a 512Mx8bit with spare 16Mx8bit capacity (or
256Mx16bit with spare 8Mx16bit capacity). The device is offered
in 1.8V VCC Power Supply. Its NAND cell provides the most
cost-effective solution for the solid state mass storage market.
The memory is divided into blocks that can be erased
independently so it is possible to preserve valid data while old
data is erased.
The device contains 4096 blocks, composed by 64 pages
consisting in two NAND structures of 32 series connected Flash
cells. A program operation allows to write the 1056-Word page in
typical 350us and an erase operation can be performed in typical
3.5ms on a 128K-Byte for X8 device block (or 64K-Word for X16
device block).
Data in the page mode can be read out at 45ns cycle time per
Elite Semiconductor Memory Technology Inc.
Word. The I/O pins serve as the ports for address and command
inputs as well as data input/output. The copy back function
allows the optimization of defective blocks management: when a
page program operation fails the data can be directly
programmed in another page inside the same array section
without the time consuming serial data insertion phase. The
cache program feature allows the data insertion in the cache
register while the data register is copied into the Flash array.
This pipelined program operation improves the program
throughput when long files are written inside the memory. A
cache read feature is also implemented. This feature allows to
dramatically improving the read throughput when consecutive
pages have to be streamed out. This device includes extra
feature: Automatic Read at Power Up.
Publication Date: May 2014
Revision: 1.4
1/54

1 Page





F59D4G81A pdf, ピン配列
ESMT
F59D4G81A / F59D4G161A
Pin Description
Symbol
Pin Name
I/O0~I/O7 (x8) Data Inputs / Outputs
I/O0~I/O15 (x16)
CLE
Command Latch
Enable
ALE Address Latch Enable
Functions
The I/O pins are used to input command, address and data, and to output data
during read operations. The I/O pins float to Hi-Z when the chip is deselected
or when the outputs are disabled.
The CLE input controls the activating path for commands sent to the internal
command register. Commands are latched into the command register through
the I/O ports on the rising edge of the WE signal with CLE high.
The ALE input controls the activating path for addresses sent to the internal
address registers. Addresses are latched into the address register through the
I/O ports on the rising edge of WE with ALE high.
CE Chip Enable
The CE input is the device selection control. When the device is in the Busy
state, CE high is ignored, and the device does not return to standby mode in
program or erase operation. Regarding CE control during read operation,
refer to ’Page read’ section of Device operation.
RE Read Enable
The RE input is the serial data-out control, and when it is active low, it drives
the data onto the I/O bus. Data is valid tREA after the falling edge of RE which
also increments the internal column address counter by one.
WE Write Enable
The WE input controls writes to the I/O port. Commands, address and data
are latched on the rising edge of the WE pulse.
WP Write Protect
The WP pin provides inadvertent program/erase protection during power
transitions. The internal high voltage generator is reset when the WP pin is
active low.
R /B
Ready / Busy Output
The R/ B output indicates the status of the device operation. When low, it
indicates that a program, erase or random read operation is in process and
returns to high state upon completion. It is an open drain output and does not
float to Hi-Z condition when the chip is deselected or when outputs are
disabled.
VCC Power
VSS Ground
NC No Connection
VCC is the power supply for device.
Lead is not internally connected.
Note: Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.4
3/54


3Pages


F59D4G81A 電子部品, 半導体
ESMT
F59D4G81A / F59D4G161A
Product Introduction
The device is a 4,224Mbit memory organized as 64K rows (pages) by 2,112x8 columns. Spare 64x8 columns are located from column
address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommodating data transfer between the I/O
buffers and memory during page read and page program operations. The program and read operations are executed on a page basis,
while the erase operation is executed on a block basis. The memory array consists of 4,096 separately erasable 128K-byte blocks. It
indicates that the bit-by-bit erase operation is prohibited on the device.
The device has addresses multiplexed into 8 or 16 I/Os . This scheme dramatically reduces pin counts and allows system upgrades to
future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by
bringing WE to low while CE is low. Those are latched on the rising edge of WE . Command Latch Enable (CLE) and Address
Latch Enable (ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle.
For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and
block erase and page program, require two cycles: one cycle for setup and the other cycle for execution.
In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
page without need for transporting the data to and from the external buffer memory.
Command Set
Function
1st Cycle
2nd Cycle
Acceptable Command
during Busy
Read
00h 30h
Read for Copy Back
00h 35h
Read ID
Reset
90h -
FFh -
O
Page Program
80h 10h
Copy-Back Program
85h 10h
Block Erase
Random Data Input(1)
Random Data Output(1)
Read Status
Read Status 2
Two-Plane Read(3)
60h
85h
05h
70h
F1h
60h-60h
D0h
-
E0h
-
-
30h
O
O
Two-Plane Read for Copy-Back
Two-Plane Random Data Output (1)(3)
Two-Plane Page Program(2)
Two-Plane Copy-Back Program(2)
60h-60h
00h-05h
80h-11h
85h-11h
35h
E0h
81h-10h
81h-10h
Two-Plane Block Erase
60h-60h
D0h
Cache Program
80h 15h
Cache Read
31h -
Read Start For Last Page Cache Read
Two-Plane Cache Read(3)
Two-Plane Cache Program(2)
3Fh
60h-60h
80h-11h
-
33h
81h-15h
NOTE:
1. Random Data Input/Output can be executed in a page.
2. Any command between 11h and 80h/81h/85h is prohibited except 70h/F1h and FFh.
3. Two-Plane Random Data Output must be used after Two-Plane Read operation or Two-Plane Cache Read operation.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.4
6/54

6 Page



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部品番号部品説明メーカ
F59D4G81A

4 Gbit (512M x 8 / 256M x 16) 1.8V NAND Flash Memory

Elite Semiconductor
Elite Semiconductor


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