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PDF F25L08QA Data sheet ( Hoja de datos )
| Número de pieza | F25L08QA | |
| Descripción | 8 Mbit Serial Flash Memory | |
| Fabricantes | Elite Semiconductor | |
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ESMT
Flash
FEATURES
Single supply voltage 2.7~3.6V
Standard, Dual and Quad SPI
Speed
- Read max frequency: 33MHz
- Fast Read max frequency: 50MHz / 86MHz / 100MHz
- Fast Read Dual/Quad max frequency: 50MHz / 86MHz /
100MHz
(100MHz / 172MHz / 200MHz equivalent Dual SPI;
200MHz / 344MHz / 400MHz equivalent Quad SPI)
Low power consumption
- Active current: 25 mA (max.)
- Standby current: 25 μ A (max.)
- Deep Power Down current: 10 μ A (max.)
Reliability
- 100,000 typical program/erase cycles
- 20 years Data Retention
Program
- Page programming time: 1.5 ms (typical)
F25L08QA (2S)
8 Mbit Serial Flash Memory
with Dual and Quad
Erase
- Chip Erase time 7 sec (typical)
- 64K bytes Block Erase time 0.75 sec (typical)
- 32K bytes Block Erase time 500 ms (typical)
- 4K bytes Sector Erase time 90 ms (typical)
Page Programming
- 256 byte per programmable page
Lockable 512 bytes OTP security sector
SPI Serial Interface
- SPI Compatible: Mode 0 and Mode 3
End of program or erase detection
Write Protect ( WP )
Hold Pin ( HOLD )
All Pb-free products are RoHS-Compliant
ORDERING INFORMATION
Product ID
Speed
F25L08QA –50PG2S
F25L08QA –86PG2S
F25L08QA –100PG2S
F25L08QA –50PAG2S
F25L08QA –86PAG2S
F25L08QA –100PAG2S
F25L08QA –50HG2S
F25L08QA –86HG2S
F25L08QA –100HG2S
50MHz
86MHz
100MHz
50MHz
86MHz
100MHz
50MHz
86MHz
100MHz
Package
Comments
8-lead
SOIC
150 mil
Pb-free
8-lead
SOIC
200 mil
Pb-free
8-contact
WSON
6x5 mm
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2
1/43
1 page  
ESMT
F25L08QA (2S)
SECTOR STRUCTURE
Table 1: Sector Address Table
64KB
Block
15
14
13
12
11
10
32KB
Block
31
30
29
28
27
26
25
24
23
22
21
20
Sector
255
:
248
247
:
240
239
:
232
231
:
224
223
:
216
215
:
208
207
:
200
199
:
192
191
:
184
183
:
176
175
:
168
167
:
160
Sector Size
(Kbytes)
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
Address range
0FF000H – 0FFFFFH
:
0F8000H – 0F8FFFH
0F7000H – 0F7FFFH
:
0F0000H – 0F0FFFH
0EF000H – 0EFFFFH
:
0E8000H – 0E8FFFH
0E7000H – 0E7FFFH
:
0E0000H – 0E0FFFH
0DF000H – 0DFFFFH
:
0D8000H – 0D8FFFH
0D7000H – 0D7FFFH
:
0D0000H – 0D0FFFH
0CF000H – 0CFFFFH
:
0C8000H – 0C8FFFH
0C7000H – 0C7FFFH
:
0C0000H – 0C0FFFH
0BF000H – 0BFFFFH
:
0B8000H – 0B8FFFH
0B7000H – 0B7FFFH
:
0B0000H – 0B0FFFH
0AF000H – 0AFFFFH
:
0A8000H – 0A8FFFH
0A7000H – 0A7FFFH
:
0A0000H – 0A0FFFH
Block Address
A19 A18 A17 A16
1111
1110
1101
1100
1011
1010
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2
5/43
5 Page 
ESMT
F25L08QA (2S)
INSTRUCTIONS
Instructions are used to Read, Write (Erase and Program), and
configure the F25L08QA. The instruction bus cycles are 8 bits
each for commands (Op Code), data, and addresses. Prior to
executing any Page Program, Write Status Register, Sector
Erase, Block Erase, or Chip Erase instructions, the Write Enable
(WREN) instruction must be executed first. The complete list of
the instructions is provided in Table 5. All instructions are
synchronized off a high to low transition of CE . Inputs will be
accepted on the rising edge of SCK starting with the most
significant bit. CE must be driven low before an instruction is
entered and must be driven high after the last bit of the instruction
has been shifted in (except for Read, Read ID, Read Status
Register, Read Electronic Signature instructions). Any low to high
transition on CE , before receiving the last bit of an instruction
bus cycle, will terminate the instruction in progress and return the
device to the standby mode.
Instruction commands (Op Code), addresses, and data are all
input from the most significant bit (MSB) first.
Table 5: Device Operation Instruction
Operation
Max.
Freq
1
SIN SOUT
Read
33 MHz 03H Hi-Z
Fast Read
Fast Read Dual Output12,13
Fast Read Dual I/O12, 14
0BH Hi-Z
3BH
BBH
Fast Read Quad
Output12, 15
Fast Read Quad I/O12, 16
Sector Erase4 (4K Byte)
Block Erase5 (32K Byte)
Block Erase5 (64K Byte)
6BH
EBH
20H Hi-Z
52H Hi-Z
D8H Hi-Z
Chip Erase
60H /
C7H
Hi-Z
Erase Suspend
75H Hi-Z
Erase Resume
7AH Hi-Z
2
SIN SOUT
A23-A16 Hi-Z
A23-A16 Hi-Z
A23-A16
A23-A8
A23-A16
A23-A0, M7-M0
A23-A16 Hi-Z
A23-A16 Hi-Z
A23-A16 Hi-Z
--
--
--
Bus Cycle 1~3
34
SIN SOUT
A15-A8 Hi-Z
A15-A8 Hi-Z
A15-A8
A7-A0, M7-M0
SIN SOUT
A7-A0 Hi-Z
A7-A0 Hi-Z
A7-A0
DOUT0~1
A15-A8
A7-A0
X, DOUT0~1
A15-A8 Hi-Z
A15-A8 Hi-Z
A15-A8 Hi-Z
DOUT2~6
A7-A0 Hi-Z
A7-A0 Hi-Z
A7-A0 Hi-Z
- ---
- ---
- ---
Page Program (PP)
50MHz 02H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z
Quad Page Program17
32H
Mode Bit Reset 6
Deep Power Down (DP)
~ FFH
B9h
Read Status Register-1
(RDSR-1) 7
05H
Read Status Register-2
(RDSR-2) 7
100MHz 35H
Write Status Register
(WRSR) 10
Write Enable (WREN) 10
01H
06H
Write Disable (WRDI)/ Exit
secured OTP mode
04H
Enter secured OTP mode
(ENSO)
B1H
Release from Deep Power
Down (RDP)
ABH
Read Electronic Signature
(RES) 8
ABH
RES in secured OTP mode
& not lock down
ABH
RES in secured OTP mode
& lock down
ABH
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
A23-A16
FFH Hi-Z
--
X
DOUT
(S7-S0)
X
DOUT
(S15-S8)
DIN
(S7-S0)
Hi-Z
--
--
--
--
XX
XX
XX
A15-A8
--
--
--
--
--
--
--
--
--
XX
XX
XX
A7-A0
--
--
--
--
-. -
--
--
-. -
--
XX
XX
XX
5
SIN SOUT
X DOUT0
XX
X
cont.
6
SIN SOUT
X DOUT1
X DOUT0
DOUT0~1
-
N
SIN SOUT
X cont.
X cont.
cont.
-
X
cont.
--
--
--
DOUT0~3
-
--
--
--
cont.
-
--
--
--
------
--
--
DIN0 Hi-Z
DIN0~3
--
--
--
--
DIN1 Hi-Z
DIN4~7
--
--
--
--
Up to
256 Hi-Z
bytes
Up to 256
byte
--
--
------
------
------
------
------
------
------
X 13H - - - -
X 33H - - - -
X 73H - - - -
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2
11/43
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet F25L08QA.PDF ] | |
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