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F25L04PA の電気的特性と機能

F25L04PAのメーカーはElite Semiconductorです、この部品の機能は「3V Only 4 Mbit Serial Flash Memory」です。


製品の詳細 ( Datasheet PDF )

部品番号 F25L04PA
部品説明 3V Only 4 Mbit Serial Flash Memory
メーカ Elite Semiconductor
ロゴ Elite Semiconductor ロゴ 




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F25L04PA Datasheet, F25L04PA PDF,ピン配置, 機能
ESMT
Flash
F25L04PA
3V Only 4 Mbit Serial Flash Memory
with Dual Output
FEATURES
Single supply voltage 2.3~3.6V
Standard, Dual SPI
Speed
- Read max frequency: 33MHz
- Fast Read max frequency: 50MHz; 86MHz; 100MHz
- Fast Read Dual max frequency: 50MHz / 86MHz/ 100MHz
(100MHz / 172MHz/ 200MHz equivalent Dual SPI)
Low power consumption
- Active current: 25 mA
- Standby current: 30 μ A
- Deep Power Down current: 5 μ A
Reliability
- 100,000 typical program/erase cycles
- 20 years Data Retention
Program
- Byte programming time: 7 μ s (typical)
- Page programming time: 1.5 ms (typical)
Erase
- Chip erase time 3.5 sec (typical)
- Block erase time 0.75 sec (typical)
- Sector erase time 150 ms (typical)
Page Programming
- 256 byte per programmable page
SPI Serial Interface
- SPI Compatible: Mode 0 and Mode 3
End of program or erase detection
Write Protect ( WP )
Hold Pin ( HOLD )
All Pb-free products are RoHS-Compliant
ORDERING INFORMATION
Product ID
F25L04PA –50PG
F25L04PA –86PG
F25L04PA –100PG
F25L04PA –50PAG
F25L04PA –86PAG
F25L04PA –100PAG
F25L04PA –50DG
F25L04PA –86DG
F25L04PA –100DG
F25L04PA –50HG
F25L04PA –86HG
F25L04PA –100HG
Speed
50MHz
86MHz
100MHz
50MHz
86MHz
100MHz
50MHz
86MHz
100MHz
50MHz
86MHz
100MHz
Package
Comments
8-lead
SOIC
150 mil
Pb-free
8-lead
SOIC
200 mil
Pb-free
8-pin
PDIP
300 mil
Pb-free
8-contact
WSON
6x5 mm
Pb-free
GENERAL DESCRIPTION
The F25L04PA is a 4Megabit, 3V only CMOS Serial Flash
memory device. The device supports the standard Serial
Peripheral Interface (SPI), and a Dual SPI. ESMT’s memory
devices reliably store memory data even after 100,000
programming and erase cycles.
The memory array can be organized into 2,048 programmable
pages of 256 byte each. 1 to 256 byte can be programmed at a
time with the Page Program instruction.
The device features sector erase architecture. The memory array
Elite Semiconductor Memory Technology Inc.
is divided into 128 uniform sectors with 4K byte each; 8 uniform
blocks with 64K byte each. Sectors can be erased individually
without affecting the data in other sectors. Blocks can be erased
individually without affecting the data in other blocks. Whole chip
erase capabilities provide the flexibility to revise the data in the
device. The device has Sector, Block or Chip Erase but no page
erase.
The sector protect/unprotect feature disables both program and
erase operations in any combination of the sectors of the
memory.
Publication Date: Aug. 2012
Revision: 1.1
1/34

1 Page





F25L04PA pdf, ピン配列
ESMT
8- Contact WSON
(WSON 8C, 6mmX5mm Body, 1.27mm Contact Pitch)
CE
SO
WP
VSS
1
2
3
4
8 VDD
7 HOLD
6 SCK
5 SI
F25L04PA
PIN DESCRIPTION
Symbol
SCK
SI
SO
CE
WP
HOLD
VDD
VSS
Pin Name
Serial Clock
Serial Data Input
Serial Data Output
Chip Enable
Write Protect
Hold
Power Supply
Ground
Functions
To provide the timing for serial input and
output operations
To transfer commands, addresses or data
serially into the device.
Data is latched on the rising edge of SCK.
To transfer data serially out of the device.
Data is shifted out on the falling edge of
SCK.
To activate the device when CE is low.
The Write Protect ( WP ) pin is used to
enable/disable BPL bit in the status
register.
To temporality stop serial communication
with SPI flash memory without resetting
the device.
To provide power.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2012
Revision: 1.1
3/34


3Pages


F25L04PA 電子部品, 半導体
ESMT
F25L04PA
STATUS REGISTER
The software status register provides status on whether the flash
memory array is available for any Read or Write operation,
whether the device is Write enabled, and the state of the memory
Write protection. During an internal Erase or Program operation,
the status register may be read only to determine the completion
of an operation in progress. Table 2 describes the function of
each bit in the software status register.
Table 2: Software Status Register
Bit Name
Function
0
BUSY
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
1
WEL
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
2 BP0 Indicate current level of block write protection (See Table 3)
3 BP1 Indicate current level of block write protection (See Table 3)
4 BP2 Indicate current level of block write protection (See Table 3)
5 TB Top / Bottom write protect
6 RESERVED Reserved for future use
7
BPL
1 = BP2,BP1,BP0 and TB are read-only bits
0 = BP2,BP1,BP0 and TB are read/writable
Note:
1. Only BP0, BP1, BP2, TB and BPL are writable.
2. BP0, BP1, BP2, TB and BPL are non-volatile.
3. All area are unprotected at power-on (BP2=BP1=BP0=0).
Default at
Power-up
0
0
0
0
0
0
0
0
Read/Write
R
R
R/W
R/W
R/W
R/W
N/A
R/W
WRITE ENABLE LATCH (WEL)
The Write-Enable-Latch bit indicates the status of the internal
memory Write Enable Latch. If this bit is set to “1”, it indicates the
device is Write enabled. If the bit is set to “0” (reset), it indicates
the device is not Write enabled and does not accept any memory
Write (Program/ Erase) commands. This bit is automatically reset
under the following conditions:
Power-up
Write Disable (WRDI) instruction completion
Page Program instruction completion
Sector Erase instruction completion
Block Erase instruction completion
Chip Erase instruction completion
Write Status Register instructions
BUSY
The Busy bit determines whether there is an internal Erase or
Program operation in progress. A “1” for the Busy bit indicates
the device is busy with an operation in progress. A “0” indicates
the device is ready for the next valid operation.
Top/Bottom Block Protect (TB)
The Top/Bottom bit (TB) controls if the Block-Protection (BP2,
BP1, BP0) bits protect from the Top (TB=0) or the Bottom (TB=1)
of the array as show in Table 3, The TB bit can be set with Write
Status Register (WRSR) instruction. The TB bit can not be written
to if the Block- Protection-Look (BPL) bit is 1 or WP is low.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2012
Revision: 1.1
6/34

6 Page



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部品番号部品説明メーカ
F25L04PA

3V Only 4 Mbit Serial Flash Memory

Elite Semiconductor
Elite Semiconductor


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