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Datasheet HXB15H1G800CF PDF ( 特性, スペック, ピン接続図 )

部品番号 HXB15H1G800CF
部品説明 1-Gbit Double-Date-Rate-Three SDRAM
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HXB15H1G800CF Datasheet, HXB15H1G800CF PDF,ピン配置, 機能
July 2014
HXB15H1G800CF
HXB15H1G160CF
1-Gbit Double-Date-Rate-Three SDRAM
DDR3 SDRAM
EU RoHS HF Compliant Products
Data Sheet
Rev. 1

1 Page



HXB15H1G800CF pdf, ピン配列
Data Sheet
1 Overview
HXB15H1G(80/16)0CF
1-Gbit Double-Data-Rate-Three SDRAM
This chapter gives an overview of the 1-Gbit Double-Data-Rate-Three SDRAM product family and describes its
main characteristics.
1.1 Features
The 1-Gbit Double-Data-Rate-Three SDRAM offers the following key features:
1.5 V ±0.075 V Power Supply
Off-Chip-Driver impedance adjustment (OCD) and
1.5 V ±0.075 V (SSTL_15) compatible I/O
DRAM organizations with 8/16 data in/outputs
Double Data Rate architecture:
two data transfers per clock cycle
eight internal banks for concurrent operation
Programmable CAS Latency: 6, 7, 8, 9, 10, 11, 12, 13
and 14 supported
Programmable Burst Length: 4/8 with both nibble
sequential and interleave mode.
Differential clock inputs (CK and CK)
Bi-directional, differential data strobes (DQS and DQS) are
transmitted / received with data. Edge aligned with read
On-Die-Termination (ODT) for better signal quality
Auto-Precharge operation for read and write bursts
Auto-Refresh, Self-Refresh and power saving Power-
Down modes
Operating temperature range 0°C to 85°C for standard use.
Operating temperature range -40°C to 85°C for industrial
use.
Average Refresh Period 7.8 μs at a TCASE lower
than 85 °C, 3.9 μs between 85 °C and 95 °C
Asynchronous RESET pin supported
TDQS (Termination Data Strobe) supported (x8 only)
Write Levelization supported 1KB page size for x8; 2KB
data and center-aligned with write data.
DLL aligns DQ and DQS transitions with clock
DQS can be disabled for single-ended data strobe
operation
Commands entered on each positive clock edge, data and
page size for x16
Packages: PG-TFBGA-78(×8)PG-TFBGA-96(×16)
RoHS Compliant, HF Products1)
All Speed grades faster than DDR3400 comply with
DDR3400 timing specifications when run at a clock rate
data mask are referenced to both edges of DQS
Data masks (DM) for write data
Posted CAS by programmable additive latency for better
of 200 MHz.
command and data bus efficiency
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as
defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances
include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
For more information please visit http://www.scsemicon.com/
Rev. 1, 2014-07
3


3Pages


HXB15H1G800CF 電子部品, 半導体
Data Sheet
2 Configuration
HXB15H1G(80/16)0CF
1-Gbit Double-Data-Rate-Three SDRAM
This chapter contains the chip configuration.
2.1 Configuration for PG-FBGA-78
The chip configuration of a DDR3 SDRAM is listed by function in Table 3. The abbreviations used in the Ball#/Buffer Type
columns are explained in Table 4 and Table 5 respectively.
Ball#
Name
Ball
Type
Clock Signals ×8 Organization
F7 CK I
G7 CK I
G9
CKE
I
Control Signals ×8 Organization
F3
RAS
I
G3
CAS
I
H3 WE I
H2 CS I
Address Signals ×8 Organization
J2 BA0 I
K8 BA1 I
J3 BA2 I
K3 A0 I
L7 A1 I
L3 A2 I
K2 A3 I
L8 A4 I
L2 A5 I
M8 A6 I
M2 A7 I
N8 A8 I
M3 A9 I
H7 A10 I
AP I
M7 A11 I
K7 A12 I
N3 A13 I
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Rev. 1, 2014-07
Function
TABLE 3
Configuration
Clock Signal CK, CK
Clock Enable
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
Chip Select
Bank Address Bus 2:0
Address Signal 13:0, Address Signal 10/Autoprecharge
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