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PDF SIS782DN Data sheet ( Hoja de datos )
| Número de pieza | SIS782DN | |
| Descripción | N-Channel 30V (D-S) MOSFET | |
| Fabricantes | Vishay | |
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SiS782DN
Vishay Siliconix
N-Channel 30 V (D-S) MOSFET with Schottky Diode
PRODUCT SUMMARY
VDS (V)
RDS(on) ()
0.0095 at VGS = 10 V
30
0.0120 at VGS = 4.5 V
ID (A)e
16
16
Qg (Typ.)
9.5 nC
PowerPAK 1212-8
3.30 mm
S
1S
3.30 mm
2
S
3
G
4
D
8D
7
D
6
D
5
Bottom View
Ordering Information:
SiS782DN-T1-GE3 (Lead (Pb)-free and Halogen-free)
FEATURES
• Halogen-free According to IEC 61249-2-21
Definition
• SkyFET® Monolithic TrenchFET® Power MOSFET
and Schottky Diode
• Low Thermal Resistance PowerPAK® Package
with Small Size and Low 1.07 mm Profile
• 100 % Rg and UIS Tested
• Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
• Notebook PC
- System Power, Memory
• Buck Converter
• Synchronous Rectifier Switch
D
G
N-Channel MOSFET
Schottky Diode
S
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter
Symbol
Limit
Unit
Drain-Source Voltage
Gate-Source Voltage
VDS
VGS
30
± 20
V
TC = 25 °C
16e
Continuous Drain Current (TJ = 150 °C)
TC = 70 °C
TA = 25 °C
ID
16e
14.5a, b
Pulsed Drain Current (t = 300 µs)
Continuous Source-Drain Diode Current
TA = 70 °C
TC = 25 °C
TA = 25 °C
IDM
IS
11.5a, b
50
16e
4a, b
A
Single Pulse Avalanche Current
Single Pulse Avalanche Energy
L = 0.1 mH
TC = 25 °C
IAS
EAS
15
11.25
41
mJ
Maximum Power Dissipation
TC = 70 °C
TA = 25 °C
PD
26
3.6a, b
W
TA = 70 °C
2.3a, b
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)c, d
TJ, Tstg
- 50 to 150
260
°C
Notes:
a. Surface mounted on 1" x 1" FR4 board.
b. t = 10 s.
c. See solder profile (www.vishay.com/ppg?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and
is not required to ensure adequate bottom side solder interconnection.
d. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
e. Package limited.
Document Number: 67954
www.vishay.com
S11-1177-Rev. A, 13-Jun-11
1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
1 page  
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
100 0.040
10 TJ = 150 °C
1
TJ = 25 °C
0.032
0.024
SiS782DN
Vishay Siliconix
ID = 10 A
0.1
0.016
TJ = 125 °C
0.01
0.001
0.0 0.2 0.4 0.6 0.8 1.0
VSD - Source-to-Drain Voltage (V)
Source-Drain Diode Forward Voltage
10-1
10-2
10-3
10-4
20 V
30 V
10-5
10-6
10 V
0.008
TJ = 25 °C
0
0 2 4 6 8 10
VGS - Gate-to-Source Voltage (V)
On-Resistance vs. Gate-to-Source Voltage
120
96
72
48
24
10-7
0
25 50 75 100 125
TJ - Temperature (°C)
Reverse Current (Schottky)
150
0
0.001
0.01
0.1
Time (s)
1
10
Single Pulse Power, Junction-to-Ambient
100
IDM Limited
ID Limited
10
100 μs
1 ms
1
Limited by RDS(on)*
0.1
10 ms
100 ms
1s
10 s
TC = 25 °C
Single Pulse
BVDSS Limited
DC
0.01
0.01
0.1
1
10 100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area, Junction-to-Ambient
Document Number: 67954
www.vishay.com
S11-1177-Rev. A, 13-Jun-11
5
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
5 Page 
AN822
Vishay Siliconix
TABLE 1: EQIVALENT STEADY STATE PERFORMANCE
Package
Configuration
SO-8
Single Dual
TSSOP-8
Single Dual
TSOP-8
Single Dual
Thermal Resiatance RthJC(C/W) 20 40 52 83 40 90
PPAK 1212
Single Dual
2.4 5.5
PPAK SO-8
Single Dual
1.8 5.5
PowerPAK 1212
49.8 °C
Standard SO-8
85 °C
Standard TSSOP-8
149 °C
TSOP-6
125 °C
2.4 °C/W
PC Board at 45 °C
20 °C/W
52 °C/W
Figure 4. Temperature of Devices on a PC Board
40 °C/W
THERMAL PERFORMANCE
Introduction
Spreading Copper
A basic measure of a device’s thermal performance is
the junction-to-case thermal resistance, Rθjc, or the
junction to- foot thermal resistance, Rθjf. This parameter
is measured for the device mounted to an infinite heat
sink and is therefore a characterization of the device
only, in other words, independent of the properties of the
object to which the device is mounted. Table 1 shows a
comparison of the PowerPAK 1212-8, PowerPAK SO-8,
standard TSSOP-8 and SO-8 equivalent steady state
performance.
By minimizing the junction-to-foot thermal resistance, the
MOSFET die temperature is very close to the tempera-
ture of the PC board. Consider four devices mounted on
a PC board with a board temperature of 45 °C (Figure 4).
Suppose each device is dissipating 2 W. Using the junc-
tion-to-foot thermal resistance characteristics of the
PowerPAK 1212-8 and the other SMT packages, die
temperatures are determined to be 49.8 °C for the Pow-
erPAK 1212-8, 85 °C for the standard SO-8, 149 °C for
standard TSSOP-8, and 125 °C for TSOP-6. This is a
4.8 °C rise above the board temperature for the Power-
PAK 1212-8, and over 40 °C for other SMT packages. A
4.8 °C rise has minimal effect on rDS(ON) whereas a rise
of over 40 °C will cause an increase in rDS(ON) as high
as 20 %.
Designers add additional copper, spreading copper, to
the drain pad to aid in conducting heat from a device. It
is helpful to have some information about the thermal
performance for a given area of spreading copper.
Figure 5 and Figure 6 show the thermal resistance of a
PowerPAK 1212-8 single and dual devices mounted on
a 2-in. x 2-in., four-layer FR-4 PC boards. The two inter-
nal layers and the backside layer are solid copper. The
internal layers were chosen as solid copper to model the
large power and ground planes common in many appli-
cations. The top layer was cut back to a smaller area and
at each step junction-to-ambient thermal resistance
measurements were taken. The results indicate that an
area above 0.2 to 0.3 square inches of spreading copper
gives no additional thermal performance improvement.
A subsequent experiment was run where the copper on
the back-side was reduced, first to 50 % in stripes to
mimic circuit traces, and then totally removed. No signif-
icant effect was observed.
Document Number 71681
03-Mar-06
www.vishay.com
3
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet SIS782DN.PDF ] | |
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