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PDF GV7600 Data sheet ( Hoja de datos )
| Número de pieza | GV7600 | |
| Descripción | Transmitter | |
| Fabricantes | Semtech | |
| Logotipo |  |
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GV7600
Aviia™ Transmitter
Key Features
• Serial digital video transmitter for standard and high
definition component video:
SD 525i and 625i
HD 720p 24, 25, 30, 50 and 60
HD 1080i 50, 60
HD 1080p 24, 25, 30, 50 and 60
• Supports 8-bit, 10-bit or 12-bit component digital
video:
RGB or YCbCr 4:4:4 sampled
YCbCr 4:2:2 or 4:2:0 sampled
• Single 75Ω coaxial cable driver output
• Integrated audio embedder for the carriage of up to 8
channels of 48kHz digital audio
• Asynchronous Serial Interface (ASI) for transmission of
IEC 13818-1 compliant transport streams
• Ancillary (ANC) data insertion
• User selectable processing features, including:
Timing Reference Signal (TRS) insertion
Programmable ANC data insertion
Illegal video code word re-mapping
• 4-wire Gennum Serial Peripheral Interface (GSPI) for
external host command and control
• Dedicated JTAG test interface
• 1.2V core and 3.3V analog voltage power supplies
• 1.8V or 3.3V selectable digital I/O power supply
• Small footprint 100-BGA (11mm x 11mm)
• Low power operation, typically 400mW
• Pb-free and RoHS compliant
Applications
• Industrial & professional cameras
• Digital video recorders (DVR)
• Video servers
• Video mixers and switchers
• Camcorders
Description
The GV7600 is a serial digital video transmitter for standard
and high definition component video. With integrated
cable driving technology, the GV7600 is capable of
transmitting digital video at 270Mb/s, 1.485Gb/s and
2.97Gb/s over 75Ω coaxial cable. The device provides a
complete transmit solution for the transmission of both
interlaced and progressive component digital video, up to
1920 x 1080, in coaxial cable-based video systems.
Using the GV7600 with the complete Aviia transmitter
reference design, it is possible to implement an all-digital,
bi-directional multimedia interface over coax. This
interface allows both DC power and a bi-directional,
half-duplex, auxiliary data interface, up to 1Mb/s, to be
carried over the same single, robust and cost effective
coaxial cable as the high-speed serial digital video.
The GV7600 includes a broad range of user-selectable
processing features, such as Timing Reference Signal (TRS)
insertion, illegal code word re-mapping, and ancillary data
packet insertion. The content of ancillary data packets can
be programmed via the host interface. Device
configuration and status reporting is accomplished via the
Gennum Serial Peripheral Interface (GSPI). Alternatively,
many processing features and operational modes can be
configured directly through external pin settings.
The device supports both 8-bit, 10-bit and 12-bit video data
input, for RGB or YCbCr 4:4:4, and YCbCr 4:2:2 or 4:2:0. A
configurable 20-bit wide parallel digital video input bus is
provided, with associated pixel clock and timing signal
inputs. The GV7600 supports direct interfacing of ITU-R
BT.656 SD formats, and HD formats conforming to ITU-R
BT.709 and BT.1120-6 for 1125-line formats, and SMPTE
296M for 750-line formats. The device may also be
configured to accepts CEA-861 timing.
The GV7600 audio embedding function allows the carriage
of up to 8 channels of serial digital audio within the
ancillary data space of the video data stream. The input
audio signal formats supported by the device include
AES/EBU for professional applications, S/PDIF, and I2S.
16-bit, 20-bit and 24-bit audio formats are supported at
GV7600
Final Data Sheet
GENDOC-051686
Rev.8
April 2014
www.semtech.com
1 of 123
Proprietary & Confidential
1 page  
4.9.1 Video Format Detection.................................................................................................... 79
4.9.2 Ancillary Data Blanking ..................................................................................................... 80
4.9.3 Ancillary Data Checksum Calculation and Insertion............................................... 81
4.9.4 TRS Generation and Insertion ......................................................................................... 81
4.9.5 HD Line Number Calculation and Insertion............................................................... 81
4.9.6 Illegal Code Re-Mapping .................................................................................................. 82
4.9.7 Line Based CRC Generation and Insertion.................................................................. 82
4.9.8 EDH Generation and Insertion........................................................................................ 82
4.9.9 Video Processing ................................................................................................................. 84
4.9.10 Processing Feature Disable ........................................................................................... 84
4.10 Parallel to Serial Conversion ...................................................................................................... 85
4.11 Serial Clock PLL .............................................................................................................................. 85
4.11.1 PLL Bandwidth ................................................................................................................... 85
4.12 Lock Detect ...................................................................................................................................... 86
4.13 Serial Digital Output .................................................................................................................... 86
4.13.1 Output Signal Interface Levels..................................................................................... 87
4.13.2 Slew Rate Selection .......................................................................................................... 88
4.13.3 Serial Digital Output Mute............................................................................................. 88
4.14 Gennum Serial Peripheral Interface ....................................................................................... 88
4.14.1 Command Word Description........................................................................................ 89
4.14.2 Data Read or Write Access............................................................................................. 90
4.14.3 GSPI Timing......................................................................................................................... 91
4.15 Host Interface Register Maps .................................................................................................... 93
4.15.1 Video Core Registers........................................................................................................ 93
4.16 SD Audio Core ..............................................................................................................................100
4.17 HD Audio Core Registers ..........................................................................................................109
4.18 Device Power-Up ........................................................................................................................116
4.19 Device Reset ..................................................................................................................................116
5. References & Relevant Standards .........................................................................................................117
6. Package & Ordering Information ..........................................................................................................118
6.1 Package Dimensions ....................................................................................................................118
6.2 Packaging Data ..............................................................................................................................119
6.3 Marking Diagram ...........................................................................................................................119
6.4 Solder Reflow Profiles ..................................................................................................................120
6.5 Ordering Information ...................................................................................................................120
GV7600
Final Data Sheet
GENDOC-051686
Rev.8
April 2014
www.semtech.com
5 of 123
Proprietary & Confidential
5 Page 
Table 1-1: Pin Descriptions (Continued)
Pin
Number
A4
A5, E1, G10,
K8
A6, B6
A7
A8
A9, D6, D7,
D8, F4
A10
B4
Name
H/HSYNC
CORE_VDD
PLL_VDD
LF
VBG
RSV
AVDD
PCLK
Timin
g
Type Description
Synch-
ronous
with
PCLK
Input
PARALLEL DATA TIMING.
Signal levels are LVCMOS / LVTTL compatible.
861_EN is LOW:
The H signal is used to indicate the portion of the video line
containing active video data, when DETECT_TRS is set LOW.
Active Line Blanking
The H signal should be LOW for the active portion of the video line.
The signal goes LOW at the first active pixel of the line, and then
goes HIGH after the last active pixel of the line.
The H signal should be set HIGH for the entire horizontal blanking
period, including both EAV and SAV TRS words, and LOW otherwise.
TRS Based Blanking (H_CONFIG = 1h)
The H signal should be set HIGH for the entire horizontal blanking
period as indicated by the H bit in the received TRS ID words, and
LOW otherwise.
861_EN = HIGH:
The HSYNC signal indicates horizontal timing. See Section 4.3.1.
When DETECT_TRS is HIGH, this pin is ignored at all times. If
DETECT_TRS is set HIGH and 861_EN is set HIGH, the DETECT_TRS
feature takes priority.
Input Power
Power supply connection for digital core logic. Connect to 1.2V DC
digital.
Input Power Power supply pin for PLL. Connect to 1.2V DC analog.
Analog
Output
Loop Filter component connection.
Output Bandgap voltage filter connection.
− These pins are reserved and should be left unconnected.
Input Power VDD for sensitive analog circuitry. Connect to 3.3VDC analog.
PARALLEL DATA BUS CLOCK.
Signal levels are LVCMOS / LVTTL compatible.
Full HD 20-bit mode
PCLK @ 148.5MHz
Full HD 10-bit mode DDR PCLK @ 148.5MHz
Input
HD 20-bit mode
HD 10-bit mode
PCLK @ 74.25MHz
PCLK @ 148.5MHz
SD 20-bit mode
PCLK @ 13.5MHz
SD 10-bit mode
PCLK @ 27MHz
ASI mode
PCLK @ 27MHz
GV7600
Final Data Sheet
GENDOC-051686
Rev.8
April 2014
www.semtech.com
11 of 123
Proprietary & Confidential
11 Page | ||
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