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ISL80113 の電気的特性と機能

ISL80113のメーカーはIntersilです、この部品の機能は「Low Input Voltage NMOS LDOs」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL80113
部品説明 Low Input Voltage NMOS LDOs
メーカ Intersil
ロゴ Intersil ロゴ 




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ISL80113 Datasheet, ISL80113 PDF,ピン配置, 機能
DATASHEET
Ultra Low Dropout 1A, 2A, 3A Low Input Voltage NMOS
LDOs
ISL80111, ISL80112, ISL80113
The ISL80111, ISL80112, and ISL80113 are ultra low dropout
LDOs providing the optimum balance between performance, size
and power consumption in size constrained designs for data
communication, computing, storage and medical applications.
These LDOs are specified for 1A, 2A and 3A of output current and
are optimized for low voltage conversions. Operating with a VIN of
1V to 3.6V and with a legacy 2.9V to 5.5V on the BIAS, the VOUT is
adjustable from 0.8V to 3.3V. With a VIN PSRR greater than 40dB
at 100kHz makes these LDOs an ideal choice in noise sensitive
applications. The guaranteed ±1.6% VOUT accuracy overall
conditions lend these parts to supplying an accurate voltage to
the latest low voltage digital ICs.
An enable input allows the part to be placed into a low quiescent
current shutdown mode. A submicron CMOS process is utilized for
this product family to deliver best-in-class analog performance
and overall value for applications in need of input voltage
conversions typically below 2.5V. It also has the superior load
transient regulation unique to a NMOS power stage. These LDOs
consume significantly lower quiescent current as a function of
load compared to bipolar LDOs.
Features
• Ultra low dropout: 75mV at 3A, (typical)
• Excellent VIN PSRR: 70dB at 1kHz (typical)
• ±1.6% guaranteed VOUT accuracy for -40ºC < TJ < +125ºC
• Very fast load transient response
• Extensive protection and reporting features
• VIN range: 1V to 3.6V, VOUT range: 0.8V to 3.3V
• Small 10 Ld 3x3 DFN package
Applications
• Noise-sensitive instrumentation and medical systems
• Data acquisition and data communication systems
• Storage, telecommunications and server equipment
• Low voltage DSP, FPGA and ASIC core power supplies
• Post-regulation of switched mode power supplies
Related Literature
UG009, “ISL8011xEVAL1Z Evaluation Board User Guide”
1.2V ±5%
VIN
CIN
10µF
ISL80111, ISL80112, ISL80113
9 VIN
10 VIN
VOUT 1
VOUT 2
3.3V ±10%
VBIAS
CBIAS
1µF
4 VBIAS
PG 6
EN
7 ENABLE
ADJ 3
GND
OPEN-DRAIN COMPATIBLE
5
COUT
10µF
1.0V
VOUT
PGOOD
R1.30kΩ
R1.40kΩ
FIGURE 1. TYPICAL APPLICATION SCHEMATIC
100
90 3A
80
70
60 2A
50
40
1A
30
20
10
0 -40
25 85
TEMPERATURE (°C)
125
FIGURE 2. DROPOUT VOLTAGE OVER-TEMP AND IOUT
100 1.015
80
60
IOUT = 2A
40
BIAS = 5V
20 VIN = 3.3V
VOUT = 2.5V
COUT = 10µF
0100
1k
IOUT = 1A
IOUT = 3A
IOUT = 0A
10k 100k
FREQUENCY (Hz)
1M
FIGURE 3. VIN PSRR vs LOAD CURRENT (ISL80113)
1.010
1.005
1.000
0.995
0.990
0.985
-40 0 25 85
TEMPERATURE (°C)
FIGURE 4. VADJ vs TEMPERATURE
125
September 30, 2016
FN7841.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2013, 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

1 Page





ISL80113 pdf, ピン配列
ISL80111, ISL80112, ISL80113
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
VOUT
(V)
TEMP RANGE
(°C)
PACKAGE
(RoHS COMPLIANT)
PKG
DWG. #
ISL80111IRAJZ
1ADJ
ADJ
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80112IRAJZ
2ADJ
ADJ
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80113IRAJZ
3ADJ
ADJ
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80111EVAL1Z
ISL80111 Evaluation Board
ISL80112EVAL1Z
ISL80112 Evaluation Board
ISL80113EVAL1Z
ISL80113 Evaluation Board
NOTES:
1. Add “-T” suffix for 6k unit or “-T7A” suffix for 250 unit tape and reel options. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information pages for ISL80111, ISL80112, and ISL80113. For more information on MSL
please see Tech Brief TB363.
TABLE 1. KEY DIFFERENCE BETWEEN FAMILY OF PARTS
PART NUMBER
ISL80111
IOUT MAXIMUM
1A
ISL80112
2A
ISL80113
3A
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3
FN7841.3
September 30, 2016


3Pages


ISL80113 電子部品, 半導体
ISL80111, ISL80112, ISL80113
Electrical Specifications Unless otherwise specified, VIN = 3V, VBIAS = 5.5V, VOUT = 0.5V, TJ = +25°C, IL = 0mA. Applications must follow
thermal guidelines of the package to determine worst-case junction temperature. Please refer to “Power Dissipation” on page 13 and Tech Brief TB379.
Boldface limits apply across junction temperature (TJ) range, -40°C to +125°C. Pulse load techniques used by ATE to ensure TJ = TA where datasheet
limits are defined. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN MAX
(Note 9) TYP (Note 9) UNIT
PG Flag Leakage Current
PG Flag Sink Current
PG = 5V, VBIAS = 5.5V
11 300
nA
7 10
mA
NOTES:
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
10. Dropout is defined by the difference in supply (VIN, VBIAS) and VOUT when the supply produces a 2% drop in VOUT from its nominal value, output
voltage set to 2.5V.
11. For normal operation, VIN must always be less than or equal to the voltage applied to VBIAS and not greater than 3.6V. Part is protected against fault
conditions where VIN can be greater than VBIAS.
Typical Operating Performance Unless otherwise noted, VIN = 1.8V, VBIAS = 3.3V, VOUT = 1.2V, CIN = COUT = 10µF,
TJ = +25°C, ILOAD = 0A.
100
90 3A VBIAS = 3.3V
80
70
3A VBIAS = 5V
2A VBIAS = 3.3V
60
50
40 2A VBIAS = 5V
30
20
10
1A VBIAS = 5V
1A VBIAS = 3.3V
0 -40 25 125
TEMPERATURE (°C)
FIGURE 6. DROPOUT vs TEMPERATURE
18
16
14
12
10
8
6
4
2
0 500.0 500.5 501.0 501.5 502.0 502.5 503.0 503.5 504.0
VADJ AT +25°C (mV)
FIGURE 7. VADJ DISTRIBUTION
1.015
1.010
1.005
1.000
0.995
0.990
0.985
-40 0
25 85
TEMPERATURE (°C)
FIGURE 8. VADJ vs TEMPERATURE
125
0.00
-0.10
-0.20
-0.30
-0.40
-0.50
-0.60
-0.70
-0.80
-0.90
-1.00
-40
IOUT = 0A TO 3A
0 25 85
TEMPERATURE (°C)
125
FIGURE 9. LOAD REGULATION vs TEMPERATURE
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6
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September 30, 2016

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共有リンク

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