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ISL54406 の電気的特性と機能

ISL54406のメーカーはIntersilです、この部品の機能は「Stereo Click and Pop Eliminator」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL54406
部品説明 Stereo Click and Pop Eliminator
メーカ Intersil
ロゴ Intersil ロゴ 




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ISL54406 Datasheet, ISL54406 PDF,ピン配置, 機能
Stereo Click and Pop Eliminator with Audio Muting
ISL54406
The Intersil ISL54406 is a Dual SPST (Single Pole/Single
Throw) switch that provides a very low distortion audio
path for a stereo headphone or high impedance line-in
load. This path can be interrupted to provide >110dB of
off-isolation for signal muting purposes into 32Ω or high
impedance loads such as consumer entertainment
system line-inputs, MP3 docking systems for powered
speaker or automotive entertainment system in-line or
cassette interfaces. Recovery from muting is instant
even with very large DC blocking capacitors.
The ISL54406 also has comprehensive Click and Pop
elimination measures to prevent these artifacts from
occurring in the load due to system power-up/power-
down, codec enable/disable, headphone hot plug in,
and audio muting on/off situations. The Click and Pop
elimination is effective into low and high impedance
loads and requires no external timing components to
deal with DC blocking capacitors placed between the
single supply codec and the load.
The ISL54406 is available in a 10 Ld TDFN (3mmx3mm)
or a tiny 10 Ld µTQFN (1.8mmx1.4mm) ultra-thin
package. It operates over a temperature range of -40 to
+85°C.
Features
• Single Supply Operation (VDD) . . . . +2.7V to +5.0V
• Negative Signal Swing Capability . . . . . . . . . . . -1.5V
• Low THD
- THD+N at 1mW into 32Ω Load. . . . . . . . . <0.02%
• Click and Pop Elimination . . . . . . . . . . . . . . . >60dB
• Audio Muting . . . . . . . . . . . . . . . . . . . . . . >110dB
• Low Power Consumption. . . . . . 21µW with 3V supply
• Low Power Shutdown Mode
• 1.8V Logic Compatible
• Available in 10 Ld TDFN (3mmx3mm) or tiny
10 Ld (1.8mmx1.4mm) µTQFN Package
• Pb-Free (RoHS Compliant)
Applications
• Consumer Entertainment Systems
• MP3 and other Personal Media Players
• Cellular/Mobile Phones
• PDA’s
• Audio Switching and Muting
Related Literature*(see page 14)
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”.
• Application Note AN1368 “ISL54406EVAL1Z
Evaluation Board User’s Manual”
Application Block Diagram
3.3V
0.1µF
VDD
LOGIC
CONTROL
LOUT
µCONTROLLER
SEL1
SEL2
LIN
AUDIO
CODEC
ROUT
CLICK AND POP
CIRCUITRY
RIN
ISL54406
GND
July 14, 2010
FN6578.1
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 Page





ISL54406 pdf, ピン配列
ISL54406
Ordering Information
PART
NUMBER
PART MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL54406IRUZ-T (Notes 2, 3)
6
-40 to +85
10 Ld 1.8x1.4 µTQFN
L10.1.8x1.4A
ISL54406IRTZ (Note 4)
4406
-40 to +85
10 Ld 3x3 TDFN
L10.3x3A
ISL54406IRTZ-T (Notes 2, 4)
4406
-40 to +85
10 Ld 3x3 TDFN
L10.3x3A
ISL54406EVAL1Z
Evaluation Board
NOTES:
2. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach
materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
5. For Moisture Sensitivity Level (MSL), please see device information page for ISL54406. For more information on MSL please
see techbrief TB363.
3 FN6578.1
July 14, 2010


3Pages


ISL54406 電子部品, 半導体
ISL54406
Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: VDD = +3.0V, GND = 0V, VSELx_H = 1.4V,
VSELx_L= 0.5V, (Notes 11), Unless Otherwise Specified (Continued)
Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
PARAMETER
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 12, 13) TYP (Notes 12, 13) UNITS
Input High Current, ISEL2H, VDD = 3.6V, VSEL2 = 3.6V, VSEL1 = 3.6V Full -2 1
ISEL1H
2
µA
SEL1 Pull-Down Resistor,
VDD = 3.6V, VSEL2 = 3.6V, VSEL1 = 0V
Full
-
4
-
MΩ
RSEL1
SEL2 Pull-Down Resistor,
VDD = 3.6V, VSEL2 = 0V, VSEL1 = 3.6V
Full
-
4
-
MΩ
RSEL2
NOTES:
11. VSELx = Input voltage to perform proper function.
12. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this
data sheet.
13. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
14. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal
range.
15. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel
with lowest max rON value.
16. Limits established by characterization and are not production tested.
17. Click and Pop Reduction specifications are limited by test equipment.
Test Circuits and Waveforms
VSEL2H
LOGIC
INPUT
VSEL2L
SWITCH
INPUT
VINPUT
SWITCH
OUTPUT 0V
50%
tOFF
VOUT
90%
tON
tr < 20ns
tf < 20ns
90%
VDD
0.1µF
VLIN/RIN
SWITCH
INPUT
SEL1
IN
SEL2
VSEL2
GND
VLOUT/ROUT
OUT
RL CL
50Ω 10pF
Repeat test for all switches. CL includes fixture and stray
capacitance.
VOUT = V(INPUT) R-----L----R-+----Lr---O----N--
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
6 FN6578.1
July 14, 2010

6 Page



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