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PDF ISO1H812G Data sheet ( Hoja de datos )
| Número de pieza | ISO1H812G | |
| Descripción | Galvanic Isolated 8 Channel High-Side Switch | |
| Fabricantes | Infineon | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ISO1H812G (archivo pdf) en la parte inferior de esta página. Total 23 Páginas | ||
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ISOFACE™
ISO1H812G
Galvanic Isolated 8 Channel High-Side Switch
Datasheet
Revision 2.6, 2014-10-17
Power Management & Multimarket
1 page  
ISOFACE™
ISO1H812G
Pin Configuration and Functionality
1 Pin Configuration and Functionality
1.1 Pin Configuration
Vbb
Pin Symbol Function
1 N.C. Not connected
N.C.
VCC
1
2
TAB
36 OUT0
35 OUT0
2 VCC Positive 3.3/5V logic supply
3 DIS Output disable
4 CS Chip select
5 SCLK Serial Clock
6 SI Serial Data input
7 N.C. Not connected
8 N.C. Not connected
9 N.C. Not connected
10 N.C. Not connected
DIS
CS
SCLK
SI
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
3
4
5
6
7
8
9
10
11
12
34 OUT1
33 OUT1
32 OUT2
31 OUT2
30 OUT3
29 OUT3
28 OUT4
27 OUT4
26 OUT5
25 OUT5
11 N.C. Not connected
12 N.C. Not connected
13 SO Serial Data Output
14 DIAG Common diagnostic output
15 GNDCC Input logic ground
16 N.C. Not connected
17 N.C. Not connected
18 N.C. Not connected
SO
DIAG
GNDCC
N.C.
N.C.
N.C.
13
14
15
16
17
18
TAB
24 OUT6
23 OUT6
22 OUT7
21 OUT7
20 N.C.
19 GNDbb
Vbb
Figure 1 Power SO-36 (430mil)
19 GNDbb Output driver ground
.
20 N.C Not connected
21 OUT7 High-side output of channel 7
22 OUT7 High-side output of channel 7
23 OUT6 High-side output of channel 6
24 OUT6 High-side output of channel 6
25 OUT5 High-side output of channel 5
26 OUT5 High-side output of channel 5
27 OUT4 High-side output of channel 4
28 OUT4 High-side output of channel 4
29 OUT3 High-side output of channel 3
30 OUT3 High-side output of channel 3
31 OUT2 High-side output of channel 2
32 OUT2 High-side output of channel 2
33 OUT1 High-side output of channel 1
34 OUT1 High-side output of channel 1
35 OUT0 High-side output of channel 0
36 OUT0 High-side output of channel 0
TAB Vbb Positive driver power supply voltage
Datasheet
5 Revision 2.6, 2014-10-17
5 Page 
ISOFACE™
ISO1H812G
Functional Description
3.5.2.2 Daisy-chain Configuration
The connection of different ICs and a µC as shown in
Fig. 10 is called a daisy-chain. For this type of bus-
topology only one SPI interface of the µC for two or
more ICs is needed. All ICs share the same clock and
chip select port of the SPI master. That is all ICs are
active and addressed simultaneously. The data out of
the µC is connected to the SI of the first IC in the line.
Each SO of an IC is connected to the SI of the next IC
in the line.
3.6 Transmission Failure Detection
There is a failure detection unit integrated to ensure
also a stable functionality during the integrated
coreless transformer transmission. This unit decides
whether the transmitted data is valid or not. If four times
serial data coming from the internal registers is not
accepted the output stages are switched off until the
next valid data is received.
SPI 1
CLK
Tx a1
Tx a2
SCLK
CS
SI
SO
Output lines
SPI- Interface
IC1
SCLK
CS
SI
Output lines
SPI- Interface
µC ICn
Number of adressed ICs = n
Number of necessary control and data ports = 3
All ICs are adressed by the common chip select
Figure 10 SPI bus all ICs in a “daisy chain”
configuration
The µC feeds the data bits into the SI of IC1 (first IC in
the chain). The bits coming from the SO of IC1 are
directly shifted into the SI of the next IC. As long as the
chip select is inactive (logic high) all the IC SPIs ignore
the clock (SCLK) and input signals (SI) and all outputs
(SO) are in tristate. As long as the chip select is active
the SPI register works as a simple shift register. With
each clock signal one input is shifted into the SPI
register (SI), each bit in the shift register moves one
position further within the register, and the last bit in the
SPI shift register is shifted out of SO. This is continued
as long as the chip select is active (logic low) and clock
signals are applied. The data is then only taken over to
the output buffers of each IC when the CS signal
changes to high from low and recognized as valid data
by the internal modulo counter.
Datasheet
11 Revision 2.6, 2014-10-17
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet ISO1H812G.PDF ] | |
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